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* Merge pull request #1521 from dh73/diego/memattrEddie Hung2019-12-167-48/+374
|\ | | | | Adding support for Xilinx memory attribute 'block' in single port mode.
| * Enforce non-existenceEddie Hung2019-12-161-0/+4
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| * Update docEddie Hung2019-12-161-4/+6
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| * Add another testEddie Hung2019-12-161-1/+8
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| * More sloppiness, thanks @dh73 for spottingEddie Hung2019-12-161-4/+4
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| * Accidentally commented out testsEddie Hung2019-12-161-47/+47
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| * Add unconditional match blocks for force RAMEddie Hung2019-12-162-4/+45
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| * OopsEddie Hung2019-12-161-4/+1
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| * Merge blockram testsEddie Hung2019-12-163-47/+81
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| * Update xc7/xcu bram rulesEddie Hung2019-12-161-8/+4
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| * Implement 'attributes' grammarEddie Hung2019-12-161-80/+88
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| * Merge branch 'diego/memattr' of https://github.com/dh73/yosys into diego/memattrEddie Hung2019-12-164-1/+238
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| * Fixing compiler warning/issues. Moving test script to the correct placeDiego H2019-12-162-14/+14
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| * Removing fixed attribute value to !ramstyle rulesDiego H2019-12-152-3242/+4
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| * Merging attribute rules into a single match block; Adding testsDiego H2019-12-155-86/+3465
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| * Refactoring memory attribute matching based on IEEE 1364.1 and Tool specificDiego H2019-12-132-0/+96
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* | Merge pull request #1575 from rodrigomelo9/masterEddie Hung2019-12-153-4/+4
|\ \ | | | | | | Fixed some missing "verilog_" in documentation
| * | Fixed some missing "verilog_" in documentationRodrigo Alejandro Melo2019-12-133-4/+4
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* | | Merge pull request #1577 from gromero/for-yosysEddie Hung2019-12-151-1/+1
|\ \ \ | | | | | | | | manual: Fix text in Abstract section
| * | | manual: Fix text in Abstract sectionGustavo Romero2019-12-111-1/+1
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* | | | Merge pull request #1578 from noopwafel/eqneq-debugEddie Hung2019-12-151-1/+1
|\ \ \ \ | |_|_|/ |/| | | Fix opt_expr.eqneq.cmpzero debug print
| * | | Fix opt_expr.eqneq.cmpzero debug printAlyssa Milburn2019-12-151-1/+1
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* | | Merge pull request #1533 from dh73/bram_xilinxEddie Hung2019-12-133-6/+101
|\ \ \ | |_|/ |/| | Adjust Xilinx xc7/xcu BRAM min bits threshold for RAMB18E1
| * | Renaming BRAM memory tests for the sake of uniformityDiego H2019-12-132-6/+6
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| * | Fixing citation in xc7_xcu_brams.txt file. Fixing RAMB36E1 test.Diego H2019-12-122-7/+7
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| * | Adding a note (TODO) in the memory_params.ys check fileDiego H2019-12-121-0/+2
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| * | Updating RAMB36E1 thresholds. Adding test for both RAMB18E1/RAMB36E1Diego H2019-12-123-2/+92
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| * | Merge https://github.com/YosysHQ/yosys into bram_xilinxDiego H2019-12-1243-1053/+2108
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| * | | Adjusting Vivado's BRAM min bits threshold for RAMB18E1Diego H2019-11-271-2/+5
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* | | | abc9_map.v: fix Xilinx LUTRAMEddie Hung2019-12-121-6/+6
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* | | Update README.md :: abc_ -> abc9_Eddie Hung2019-12-111-3/+3
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* | | Fix bitwidth mismatch; suppresses iverilog warningEddie Hung2019-12-111-4/+4
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* | | Merge pull request #1564 from ZirconiumX/intel_housekeepingDavid Shah2019-12-118-6/+6
|\ \ \ | | | | | | | | Intel housekeeping
| * | | synth_intel: a10gx -> arria10gxDan Ravensloft2019-12-105-4/+4
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| * | | synth_intel: cyclone10 -> cyclone10lpDan Ravensloft2019-12-105-4/+4
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* | | | Merge pull request #1545 from YosysHQ/eddie/ice40_wrapcarry_attrEddie Hung2019-12-098-51/+225
|\ \ \ \ | | | | | | | | | | Preserve SB_CARRY name and attributes when using $__ICE40_CARRY_WRAPPER
| * | | | ice40_opt to restore attributes/name when unwrappingEddie Hung2019-12-091-0/+15
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| * | | | ice40_wrapcarry -unwrap to preserve 'src' attributeEddie Hung2019-12-091-1/+9
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| * | | | unmap $__ICE40_CARRY_WRAPPER in testEddie Hung2019-12-091-1/+21
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| * | | | -unwrap to create $lut not SB_LUT4 for opt_lutEddie Hung2019-12-091-7/+5
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| * | | | Sensitive to direct inst of $__ICE40_CARRY_WRAPPER; recreate SB_LUT4Eddie Hung2019-12-092-8/+12
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| * | | | ice40_wrapcarry to really preserve attributes via -unwrap optionEddie Hung2019-12-094-39/+61
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| * | | | Drop keep=0 attributes on SB_CARRYEddie Hung2019-12-062-2/+10
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| * | | | Merge SB_CARRY+SB_LUT4's attributes when creating $__ICE40_CARRY_WRAPPEREddie Hung2019-12-051-0/+1
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| * | | | Add WIP test for unwrapping $__ICE40_CARRY_WRAPPEREddie Hung2019-12-051-0/+30
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| * | | | Check SB_CARRY name also preservedEddie Hung2019-12-031-0/+1
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| * | | | $__ICE40_CARRY_WRAPPER to use _TECHMAP_REPLACE_ for SB_CARRY to preserveEddie Hung2019-12-031-1/+1
| | | | | | | | | | | | | | | | | | | | name and attr
| * | | | ice40_opt to ignore (* keep *) -ed cellsEddie Hung2019-12-031-0/+5
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| * | | | ice40_wrapcarry to preserve SB_CARRY's attributesEddie Hung2019-12-031-0/+2
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| * | | | Add testcaseEddie Hung2019-12-031-0/+60
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