| Commit message (Collapse) | Author | Age | Files | Lines | ||
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| * | | Added ast.h to exported headers | Clifford Wolf | 2016-03-22 | 1 | -0/+1 | |
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| * | | Cleanup abstract modules at end of "hierarchy -top" | Clifford Wolf | 2016-03-21 | 1 | -2/+0 | |
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| * | | Support for abstract modules in chparam | Clifford Wolf | 2016-03-21 | 1 | -0/+6 | |
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| * | | Added support for $stop system task | Clifford Wolf | 2016-03-21 | 1 | -5/+5 | |
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| * | | Improvements in synth_greenpak4, added -part option | Clifford Wolf | 2016-03-21 | 1 | -30/+25 | |
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| * | | Improvements in ABCEXTERNAL handling | Clifford Wolf | 2016-03-19 | 3 | -11/+18 | |
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| * | | Merge pull request #130 from ravenexp/master | Clifford Wolf | 2016-03-19 | 2 | -4/+16 | |
| |\ \ | | | | | | | Support calling out to an external ABC. | |||||
| | * | | Support calling out to an external ABC. | Sergey Kvachonok | 2016-03-19 | 2 | -4/+16 | |
| |/ / | | | | | | | | | | | | | $ make ABCEXTERNAL=my-abc && make ABCEXTERNAL=my-abc install configures yosys to use an external ABC executable instead of building and installing the in-tree ABC copy (yosys-abc). | |||||
| * | | Added $display %m support, fixed mem leak in $display, fixes #128 | Clifford Wolf | 2016-03-19 | 1 | -20/+44 | |
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| * | | Added black box modules for all the 7-series design elements (as listed in ↵ | Clifford Wolf | 2016-03-19 | 4 | -0/+3441 | |
| | | | | | | | | | ug953) | |||||
| * | | Fixed localparam signdness, fixes #127 | Clifford Wolf | 2016-03-18 | 1 | -1/+1 | |
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| * | | Set "nosync" attribute on internal task/function wires | Clifford Wolf | 2016-03-18 | 1 | -0/+1 | |
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| * | | Fixed Verilog parser fix and more similar improvements | Clifford Wolf | 2016-03-15 | 1 | -18/+9 | |
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| * | | Use left-recursive rule for cell_port_list in Verilog parser. | Andrew Becker | 2016-03-15 | 1 | -6/+10 | |
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| * | | Bugfix in write_verilog for RTLIL processes | Clifford Wolf | 2016-03-14 | 1 | -9/+20 | |
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| * | | Cleanups and improvements in examples/cmos/ | Clifford Wolf | 2016-03-11 | 5 | -12/+19 | |
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| * | | Merge commit 'b34385ec924b6067c1f82bdbae923f8062518956' | Clifford Wolf | 2016-03-11 | 5 | -9/+76 | |
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| | * | | Completed ngspice digital example with verilog tb | Uros Platise | 2016-03-05 | 5 | -9/+76 | |
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| * | | | Fixed typos in verilog_defaults help message | Clifford Wolf | 2016-03-10 | 1 | -3/+3 | |
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| * | | | Added "write_edif -nogndvcc" | Clifford Wolf | 2016-03-08 | 1 | -17/+34 | |
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| * | | | Added examples/cxx-api/evaldemo.cc | Clifford Wolf | 2016-03-08 | 1 | -0/+55 | |
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| * | | | Merge branch 'master' of github.com:cliffordwolf/yosys | Clifford Wolf | 2016-03-07 | 7 | -25/+123 | |
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| | * | | Added digital (xspice) example code to examples/cmos/ | Clifford Wolf | 2016-03-02 | 4 | -1/+70 | |
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| | * | | Be more conservative with net names in spice output | Clifford Wolf | 2016-03-02 | 1 | -18/+47 | |
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| | * | | Merge pull request #119 from SebKuzminsky/spelling-fixes | Clifford Wolf | 2016-02-29 | 2 | -6/+6 | |
| | |\ \ | | | | | | | | | user-facing spelling fixes | |||||
| | | * | | user-facing spelling fixes | Sebastian Kuzminsky | 2016-02-28 | 2 | -6/+6 | |
| | |/ / | | | | | | | | | | | | | "speciefied" -> "specified" "unkown" -> "unknown" | |||||
| * / / | Using "mfs" and "lutpack" in ABC lut mapping | Clifford Wolf | 2016-03-07 | 1 | -5/+14 | |
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| * | | We are now in 0.6+ development | Clifford Wolf | 2016-02-26 | 1 | -1/+1 | |
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| * | | Yosys 0.6 | Clifford Wolf | 2016-02-26 | 1 | -1/+1 | |
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| * | | Fixed BLIF parser for empty port assignments | Clifford Wolf | 2016-02-24 | 1 | -2/+2 | |
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| * | | Use easyer-to-read unoptimized ceil_log2() | Clifford Wolf | 2016-02-15 | 1 | -18/+5 | |
| | | | | | | | | | | | see here for details on the optimized version: http://svn.clifford.at/handicraft/2016/esbmc/ceilog2.c | |||||
| * | | Updated ABC to ae7d65e71adc | Clifford Wolf | 2016-02-15 | 1 | -1/+1 | |
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| * | | Updated command reference in manual | Clifford Wolf | 2016-02-14 | 3 | -16/+364 | |
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| * | | Changelog for upcoming 0.6 release | Clifford Wolf | 2016-02-14 | 1 | -0/+88 | |
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| * | | Fixed more visual studio warnings | Clifford Wolf | 2016-02-14 | 1 | -5/+3 | |
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| * | | Fixed some visual studio warnings | Clifford Wolf | 2016-02-13 | 8 | -10/+10 | |
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| * | | Merge branch 'master' of github.com:cliffordwolf/yosys | Clifford Wolf | 2016-02-13 | 1 | -1/+1 | |
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| | * | | Fixed MXE ABC build | Clifford Wolf | 2016-02-13 | 1 | -1/+1 | |
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| * | | | Added "int ceil_log2(int)" function | Clifford Wolf | 2016-02-13 | 5 | -10/+58 | |
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| * | | Run dffsr2dff in synth_xilinx | Clifford Wolf | 2016-02-13 | 1 | -0/+2 | |
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| * | | Support for more Verific primitives (patch I got per email) | Clifford Wolf | 2016-02-13 | 1 | -1/+31 | |
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| * | | Updated ABC | Clifford Wolf | 2016-02-08 | 1 | -1/+1 | |
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| * | | Work around DDR dout sim glitches in ice40 SB_IO sim model | Clifford Wolf | 2016-02-07 | 1 | -1/+7 | |
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| * | | Updated ABC | Clifford Wolf | 2016-02-07 | 1 | -1/+1 | |
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| * | | Added "stat -liberty" for calculating chip area | Clifford Wolf | 2016-02-04 | 1 | -6/+60 | |
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| * | | Bugfix in Verific front-end | Clifford Wolf | 2016-02-03 | 1 | -2/+5 | |
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| * | | Updated verific build instructions | Clifford Wolf | 2016-02-02 | 1 | -2/+0 | |
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| * | | Improved dffsr2dff pass | Clifford Wolf | 2016-02-02 | 1 | -5/+50 | |
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| * | | Added dffsr2dff | Clifford Wolf | 2016-02-02 | 3 | -0/+171 | |
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| * | | Added addBufGate module method | Clifford Wolf | 2016-02-02 | 3 | -0/+8 | |
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index : iCE40/yosys | |
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