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* fix fsm test with proper clock enable polarityPepijn de Vos2019-11-112-4/+15
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* Merge branch 'master' of https://github.com/YosysHQ/yosys into gowinPepijn de Vos2019-11-1129-23010/+30701
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| * Merge pull request #1470 from YosysHQ/clifford/subpassdocClifford Wolf2019-11-101-0/+46
| |\ | | | | | | Add CodingReadme section on script passes
| | * Add CodingReadme section on script passesClifford Wolf2019-10-311-0/+46
| | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | Add check for valid macro names in macro definitionsClifford Wolf2019-11-071-7/+11
| | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | synth_xilinx: Merge blackbox primitive libraries.Marcin Kościelnicki2019-11-0611-23234/+29820
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | First, there are no longer separate cell libraries for xc6s/xc7/xcu. Manually instantiating a primitive for a "wrong" family will result in yosys passing it straight through to the output, and it will be either upgraded or rejected by the P&R tool. Second, the blackbox library is expanded to cover many more families: everything from Spartan 3 up is included. Primitives for Virtex and Virtex 2 are listed in the Python file as well if we ever want to include them, but that would require having two different ISE versions (10.1 and 14.7) available when running cells_xtra.py, and so is probably more trouble than it's worth. Third, the blockram blackboxes are no longer in separate files — there is no practical reason to do so (from synthesis PoV, they are no different from any other cells_xtra blackbox), and they needlessly complicated the flow (among other things, merging them allows the user to use eg. Series 7 primitives and have them auto-upgraded to Ultrascale). Last, since xc5v logic synthesis appears to work reasonably well (the only major problem is lack of blockram inference support), xc5v is now an accepted setting for the -family option.
| * | Fix write_aiger bug added in 524af21Clifford Wolf2019-11-041-0/+3
| |/ | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * Merge pull request #1393 from whitequark/write_verilog-avoid-initClifford Wolf2019-10-271-4/+5
| |\ | | | | | | write_verilog: do not print (*init*) attributes on regs
| | * write_verilog: do not print (*init*) attributes on regs.whitequark2019-09-221-4/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If an init value is emitted for a reg, an (*init*) attribute is never necessary, since it is exactly equivalent. On the other hand, some tools that consume Verilog (ISE, Vivado, Quartus) complain about (*init*) attributes because their interpretation differs from Yosys. All (*init*) attributes that would not become reg init values anyway are emitted as before.
| * | Improve naming scheme for (VHDL) modules imported from VerificClifford Wolf2019-10-241-3/+26
| | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | Merge pull request #1455 from YosysHQ/dave/ultrascaleplusDavid Shah2019-10-249-417/+1153
| |\ \ | | | | | | | | Add BRAM and URAM mapping for UltraScale[+]
| | * | xilinx: Add URAM288 mapping for xcupDavid Shah2019-10-235-2/+92
| | | | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
| | * | xilinx: Add support for UltraScale[+] BRAM mappingDavid Shah2019-10-237-416/+1062
| | | | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
| * | | Add "verific -L"Clifford Wolf2019-10-241-1/+12
| |/ / | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | Bugfix in smtio vcd handling of $-identifiersClifford Wolf2019-10-231-6/+9
| | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | xilinx: Support multiplier mapping for all families.Marcin Kościelnicki2019-10-229-9/+269
| | | | | | | | | | | | | | | This supports several older families that are not yet supported for actual logic synthesis — the intention is to add them soon.
| * | Merge pull request #1452 from nakengelhardt/fix_dsp_mem_regClifford Wolf2019-10-222-0/+2
| |\ \ | | | | | | | | Call memory_dff before DSP mapping to reserve registers (fixes #1447)
| | * | Call memory_dff before DSP mapping to reserve registers (fixes #1447)N. Engelhardt2019-10-172-0/+2
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| * | | Add "verilog_defines -list" and "verilog_defines -reset"Clifford Wolf2019-10-211-0/+16
| | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | | Fix handling of "restrict" in Verific front-endClifford Wolf2019-10-211-1/+1
| | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | | | fix wide lutsPepijn de Vos2019-11-062-19/+22
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* | | | don't cound exact luts in big muxes; futile and fragilePepijn de Vos2019-10-301-3/+0
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* | | | add IOBUFPepijn de Vos2019-10-282-1/+10
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* | | | add tristate buffer and testPepijn de Vos2019-10-283-2/+21
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* | | | do not use wide luts in testcasePepijn de Vos2019-10-281-3/+3
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* | | | actually run the gowin testsPepijn de Vos2019-10-281-0/+1
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* | | | More formattingPepijn de Vos2019-10-281-55/+49
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* | | | really really fix formatting maybePepijn de Vos2019-10-281-41/+41
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* | | | undo formatting fuckupPepijn de Vos2019-10-281-25/+25
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* | | | add wide lutsPepijn de Vos2019-10-283-36/+119
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* | | | add 32-bit BRAM and byte-enablesPepijn de Vos2019-10-282-4/+25
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* | | | ALU sim tweaksPepijn de Vos2019-10-242-13/+13
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* | | | Add some testsPepijn de Vos2019-10-2110-0/+224
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Copied from Efinix. * fsm is broken * latch and tribuf are not implemented yet * memory maps to dram
* | | | add a few more missing dffPepijn de Vos2019-10-211-7/+16
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* | | | add negedge DFFPepijn de Vos2019-10-212-15/+139
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* | | | use ADDSUB ALU mode to remove invertersPepijn de Vos2019-10-212-7/+77
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* | | | Merge branch 'master' of https://github.com/YosysHQ/yosys into gowinPepijn de Vos2019-10-21275-2678/+32872
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| * | | ecp5: Pass -nomfs to abc9David Shah2019-10-201-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | Fixes #1459 Signed-off-by: David Shah <dave@ds0.me>
| * | | Merge pull request #1457 from xobs/python-binary-nameMiodrag Milanović2019-10-196-9/+9
| |\ \ \ | | | | | | | | | | Makefile: don't assume python is called `python3`
| | * | | Makefile: don't assume python is called `python3`Sean Cross2019-10-196-9/+9
| |/ / / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On some architectures, notably on Windows, the official name for the Python binary from python.org is `python`. The build system assumes that python is called `python3`, which breaks under this architecture. There is already infrastructure in place to determine the name of the Python binary when building PYOSYS. Since Python is now always required to build Yosys, enable this check universally which sets the `PYTHON_EXECUTABLE` variable. Then, reuse this variable in other Makefiles as necessary, rather than hardcoding `python3` everywhere. Signed-off-by: Sean Cross <sean@xobs.io>
| * | | Merge pull request #1454 from YosysHQ/mmicko/common_testsMiodrag Milanović2019-10-18166-1763/+455
| |\ \ \ | | | | | | | | | | Share common tests
| | * | | fixed errorMiodrag Milanovic2019-10-181-1/+1
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| | * | | Unify verilog styleMiodrag Milanovic2019-10-1811-191/+157
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| | * | | Common memory test now sharedMiodrag Milanovic2019-10-1810-89/+5
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| | * | | Remove not needed testsMiodrag Milanovic2019-10-184-52/+0
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| | * | | Share common testsMiodrag Milanovic2019-10-18103-1316/+178
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| | * | | fix yosys pathMiodrag Milanovic2019-10-181-2/+2
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| | * | | Fix path to yosysMiodrag Milanovic2019-10-185-5/+5
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| | * | | Moved all tests in arch sub directoryMiodrag Milanovic2019-10-18151-5/+5
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| * | | Add async2syncMiodrag Milanovic2019-10-182-8/+8
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