| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | Start restoring memory state from VCD/FST | Miodrag Milanovic | 2022-05-04 | 3 | -3/+50 |
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| * | Add propagated clock signals into btor info file | Claire Xenia Wolf | 2022-05-04 | 1 | -0/+2 |
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| * | Bump version | github-actions[bot] | 2022-05-03 | 1 | -1/+1 |
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| * | AIM file could have gaps in or between inputs and inits | Miodrag Milanovic | 2022-05-02 | 1 | -3/+6 |
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| * | Bump version | github-actions[bot] | 2022-04-30 | 1 | -1/+1 |
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| * | Merge pull request #3294 from YosysHQ/micko/verific_merge_past_ff | Miodrag Milanović | 2022-04-29 | 1 | -0/+1 |
| |\ | | | | | Ignore merging past ffs that we are not properly merging | ||||
| | * | Ignore merging past ffs that we are not properly merging | Miodrag Milanovic | 2022-04-29 | 1 | -0/+1 |
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| * | Bump version | github-actions[bot] | 2022-04-26 | 1 | -1/+1 |
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| * | Add missing parameters for ecp5 | Rick Luiken | 2022-04-25 | 2 | -1/+2 |
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| * | Merge pull request #3287 from jix/smt2-conditional-store | Jannis Harder | 2022-04-25 | 1 | -2/+4 |
| |\ | | | | | smt2: Make write port array stores conditional on nonzero write mask | ||||
| | * | smt2: Make write port array stores conditional on nonzero write mask | Jannis Harder | 2022-04-20 | 1 | -2/+4 |
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| * | | Merge pull request #3257 from jix/tribuf-formal | Jannis Harder | 2022-04-25 | 1 | -3/+46 |
| |\ \ | | | | | | | tribuf: `-formal` option: convert all to logic and detect conflicts | ||||
| | * | | tribuf: `-formal` option: convert all to logic and detect conflicts | Jannis Harder | 2022-04-12 | 1 | -3/+46 |
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| * | | | Merge pull request #3290 from mpasternacki/bugfix/freebsd-build | Miodrag Milanović | 2022-04-25 | 1 | -0/+3 |
| |\ \ \ | | | | | | | | | Fix build on FreeBSD, which has no alloca.h | ||||
| | * | | | Fix build on FreeBSD, which has no alloca.h | Maciej Pasternacki | 2022-04-24 | 1 | -0/+3 |
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| * | | | Merge pull request #3289 from YosysHQ/micko/sim_improve | Miodrag Milanović | 2022-04-25 | 2 | -29/+74 |
| |\ \ \ | |/ / |/| | | Simulation improvements | ||||
| | * | | Match $anyseq input if connected to public wire | Miodrag Milanovic | 2022-04-22 | 1 | -6/+12 |
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| | * | | Treat $anyseq as input from FST | Miodrag Milanovic | 2022-04-22 | 1 | -0/+21 |
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| | * | | Ignore change on last edge | Miodrag Milanovic | 2022-04-22 | 1 | -4/+5 |
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| | * | | Last sample from input does not represent change | Miodrag Milanovic | 2022-04-22 | 1 | -1/+2 |
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| | * | | latches are always set to zero | Miodrag Milanovic | 2022-04-22 | 1 | -6/+1 |
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| | * | | If not multiclock, output only on clock edges | Miodrag Milanovic | 2022-04-22 | 1 | -0/+18 |
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| | * | | Set init state for all wires from FST and set past | Miodrag Milanovic | 2022-04-22 | 1 | -13/+12 |
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| | * | | Fix multiclock for btor2 witness | Miodrag Milanovic | 2022-04-22 | 1 | -5/+9 |
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| * | | Bump version | github-actions[bot] | 2022-04-19 | 1 | -1/+1 |
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| * | | Merge pull request #3280 from YosysHQ/micko/fix_readaiw | Miodrag Milanović | 2022-04-18 | 2 | -3/+3 |
| |\ \ | | | | | | | Fix reading aiw from other solvers | ||||
| | * | | Update abc | Miodrag Milanovic | 2022-04-18 | 1 | -1/+1 |
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| | * | | Fix reading aiw from other solvers | Miodrag Milanovic | 2022-04-15 | 1 | -2/+2 |
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| * | | verific: allow memories to be inferred in loops (vhdl) | Miodrag Milanovic | 2022-04-18 | 1 | -0/+1 |
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| * | | Merge pull request #3282 from nakengelhardt/verific_loop_rams | Miodrag Milanović | 2022-04-18 | 1 | -0/+1 |
| |\ \ | | | | | | | verific: allow memories to be inferred in loops | ||||
| | * | | verific: allow memories to be inferred in loops | N. Engelhardt | 2022-04-15 | 1 | -0/+1 |
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| * | | Bump version | github-actions[bot] | 2022-04-16 | 1 | -1/+1 |
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| * | | memory_share: Fix up mismatched address widths. | Marcelina Kościelnicka | 2022-04-15 | 1 | -0/+14 |
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| * | | opt_dff: Fix behavior on $ff with D == Q. | Marcelina Kościelnicka | 2022-04-15 | 1 | -1/+1 |
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| * | Bump version | github-actions[bot] | 2022-04-09 | 1 | -1/+1 |
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| * | Merge pull request #3275 from YosysHQ/micko/clk2fflogic_fix | Miodrag Milanović | 2022-04-08 | 1 | -9/+11 |
| |\ | | | | | Use wrap_async_control_gate if ff is fine | ||||
| | * | Use wrap_async_control_gate if ff is fine | Miodrag Milanovic | 2022-04-08 | 1 | -9/+11 |
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| * | Merge pull request #3273 from modwizcode/fix-build | Miodrag Milanović | 2022-04-08 | 2 | -1/+12 |
| |\ | | | | | Do not enable features that require the support of compression compiled in | ||||
| | * | Makefile: properly conditionalize features requiring compression. | Iris Johnson | 2022-04-07 | 2 | -1/+12 |
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| * | | pass jny: flipped the defaults for the inclusion of various bits of metadata | Aki Van Ness | 2022-04-08 | 1 | -30/+30 |
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| * | | pass jny: ensured the cell collection is cleared between modules | Aki Van Ness | 2022-04-08 | 1 | -0/+1 |
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| * | | pass jny: fixed missing quotes around the type value for the cell sort | Aki Van Ness | 2022-04-08 | 1 | -1/+1 |
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| * | | pass jny: fixed the backslash escape for strings | Aki Van Ness | 2022-04-08 | 1 | -2/+1 |
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| * | | pass jny: removed the invalid json escapes | Aki Van Ness | 2022-04-08 | 1 | -12/+0 |
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| * | | pass jny: added some todo comments about things that need to be done before ↵ | Aki Van Ness | 2022-04-08 | 1 | -0/+5 |
| | | | | | | | | | a proper merge, but it should be enough for the PoC at the moment | ||||
| * | | pass jny: changed the constructor initializers to use parens rather than ↵ | Aki Van Ness | 2022-04-08 | 1 | -2/+2 |
| | | | | | | | | | curly-braces to hopefully make GCC 4.8 happy | ||||
| * | | pass jny: fixed the string escape method to be less jank and more proper | Aki Van Ness | 2022-04-08 | 1 | -21/+58 |
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| * | | pass jny: fixed the signed output for param value output | Aki Van Ness | 2022-04-08 | 1 | -1/+1 |
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| * | | pass jny: added connection output | Aki Van Ness | 2022-04-08 | 1 | -4/+88 |
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| * | | pass jny: added filter options for including connections, attributes, and ↵ | Aki Van Ness | 2022-04-08 | 1 | -25/+125 |
| | | | | | | | | | properties | ||||
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index : iCE40/yosys | |
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