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| | * | Remove noise from ice40/cells_sim.vEddie Hung2019-06-271-5/+0
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| | * | Refactor for one "abc_carry" attribute on moduleEddie Hung2019-06-275-82/+84
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| | * | Merge branch 'xaig' of github.com:YosysHQ/yosys into xaigEddie Hung2019-06-272-0/+19
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| | | * \ Merge remote-tracking branch 'origin/master' into xaigEddie Hung2019-06-272-0/+19
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| | * | | | Do not use Module::remove() iterator versionEddie Hung2019-06-271-5/+6
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| | * | | | Remove redundant docEddie Hung2019-06-271-3/+0
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| | * | | | Remove &retime when abc9 -fastEddie Hung2019-06-271-1/+1
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| | * | | | Cleanup abc9.ccEddie Hung2019-06-271-15/+17
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| | * | | | Undo iterator based Module::remove() for cells, as containers will notEddie Hung2019-06-272-11/+2
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| * | | | Merge pull request #1146 from gsomlo/gls-test-abc-extClifford Wolf2019-06-284-8/+29
| |\ \ \ \ | | |_|_|/ | |/| | | tests: use optional ABCEXTERNAL when specified
| | * | | tests: use optional ABCEXTERNAL when specifiedGabriel L. Somlo2019-06-274-8/+29
| | | |/ | | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commits 65924fd1, abc40924, and ebe29b66 hard-code the invocation of yosys-abc, which fails if ABCEXTERNAL was specified during the build. Allow tests to utilize an optional, externally specified abc binary. Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
| * | | Merge pull request #1046 from bogdanvuk/masterClifford Wolf2019-06-285-16/+127
| |\ \ \ | | |/ / | |/| | Optimizing DFFs whose initial value prevents their value from changing
| | * | Add help for "-sat" option inside opt_rmdff. "opt" can pass "-sat" tooBogdan Vukobratovic2019-06-272-2/+10
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| | * | Fix memory leak when one of multiple DFF cells is removed in opt_rmdffBogdan Vukobratovic2019-06-271-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | When there are multiple DFFs and one of them is removed, its reference lingers inside bit2driver dict. While invoking handle_dff() function for other DFFs, this broken reference is used isnside sat_import_cell() function.
| | * | Merge remote-tracking branch 'upstream/master'Bogdan Vukobratovic2019-06-2737-143/+1631
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| | * | | Refactor "opt_rmdff -sat"Clifford Wolf2019-06-204-373/+58
| | | | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| | * | | Merge branch 'master' of https://github.com/bogdanvuk/yosys into ↵Clifford Wolf2019-06-205-10/+423
| | |\ \ \ | | | | | | | | | | | | | | | | | | clifford/ext1046
| | | * | | Move netlist helper module to passes/opt for the time beingBogdan Vukobratovic2019-06-142-1/+1
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| | | * | | Merge remote-tracking branch 'upstream/master'Bogdan Vukobratovic2019-06-1473-475/+1352
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| | | * | | | Prepare for situation when port of the signal cannot be foundBogdan Vukobratovic2019-06-142-2/+8
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| | | * | | | Some cleanup, revert sat.ccBogdan Vukobratovic2019-06-142-13/+11
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| | | * | | | Implement disconnection of constant register bitsBogdan Vukobratovic2019-06-132-44/+109
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| | | * | | | Pass SigBit by value to Netlist algorithmsBogdan Vukobratovic2019-06-131-65/+84
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| | | * | | | Rename satgen_algo.h -> algo.h, code cleanup and refactoringBogdan Vukobratovic2019-06-124-279/+265
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| | | * | | | Generate satgen instance instead of calling sat passBogdan Vukobratovic2019-06-112-24/+129
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| | | * | | | Refactor driver map generationBogdan Vukobratovic2019-06-101-0/+158
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - Implement iterators over the driver map that enumerate signals and cells within the cones of the signal
| | | * | | | Fix the regressionBogdan Vukobratovic2019-05-281-1/+2
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| | | * | | | Merge remote-tracking branch 'upstream/master'Bogdan Vukobratovic2019-05-281-1/+11
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| | | * | | | | Optimizing DFFs whose initial value prevents their value from changingBogdan Vukobratovic2019-05-284-3/+78
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is a proof of concept implementation that invokes SAT solver via Pass::call method.
| * | | | | | | Merge pull request #1139 from YosysHQ/dave/check-sim-iverilogEddie Hung2019-06-272-0/+19
| |\ \ \ \ \ \ \ | | | | | | | | | | | | | | | | | | tests: Check that Icarus can parse arch sim models
| | * | | | | | | Add simcells.v, simlib.v, and some outputEddie Hung2019-06-271-1/+11
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| | * | | | | | | tests: Check that Icarus can parse arch sim modelsDavid Shah2019-06-262-0/+9
| | | |_|_|_|/ / | | |/| | | | | | | | | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | | | | | | | Merge branch 'xaig' into xc7muxEddie Hung2019-06-274-9/+39
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| * | | | | | | Merge remote-tracking branch 'origin/master' into xaigEddie Hung2019-06-274-9/+39
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| | * | | | | | GrrEddie Hung2019-06-271-1/+1
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| | * | | | | | CapitalisationEddie Hung2019-06-271-1/+1
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| | * | | | | | Make CHANGELOG clearerEddie Hung2019-06-271-0/+1
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| | * | | | | | Merge pull request #1143 from YosysHQ/clifford/fix1135Eddie Hung2019-06-274-8/+38
| | |\ \ \ \ \ \ | | | | | | | | | | | | | | | | | | Add "pmux2shiftx -norange"
| | | * | | | | | Add #1135 testcaseEddie Hung2019-06-272-5/+26
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| | | * | | | | | Add "pmux2shiftx -norange", fixes #1135Clifford Wolf2019-06-272-3/+12
| | | |/ / / / / | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | | | | | | | Merge remote-tracking branch 'origin/xaig' into xc7muxEddie Hung2019-06-270-0/+0
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| * | | | | | | Merge remote-tracking branch 'origin/master' into xaigEddie Hung2019-06-270-0/+0
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| | * | | | | | synth_xilinx -arch -> -family, consistent with older synth_intelEddie Hung2019-06-271-7/+8
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| | * | | | | | Merge pull request #1142 from YosysHQ/clifford/fix1132Eddie Hung2019-06-272-6/+345
| | |\ \ \ \ \ \ | | | | | | | | | | | | | | | | | | Fix handling of partial covers in muxcover
| | * \ \ \ \ \ \ Merge pull request #1138 from YosysHQ/koriakin/xc7nocarrymuxEddie Hung2019-06-272-12/+34
| | |\ \ \ \ \ \ \ | | | |_|/ / / / / | | |/| | | | | | synth_xilinx: Add -nocarry and -nowidelut options
* | | | | | | | | Merge remote-tracking branch 'origin/xaig' into xc7muxEddie Hung2019-06-271-7/+10
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| * | | | | | | | Add warning if synth_xilinx -abc9 with family != xc7Eddie Hung2019-06-271-0/+2
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| * | | | | | | | Remove unneeded includeEddie Hung2019-06-271-3/+0
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| * | | | | | | | Merge origin/masterEddie Hung2019-06-2710-65/+480
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* | | | | | | | | Merge remote-tracking branch 'origin/clifford/fix1132' into xc7muxEddie Hung2019-06-271-6/+25
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