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* Merge pull request #1186 from YosysHQ/eddie/abc9_ice40_fixEddie Hung2019-07-169-31/+122
|\ | | | | abc9/ice40: encapsulate SB_CARRY+SB_LUT4 into one box
| * $__ICE40_CARRY_LUT4 -> $__ICE40_FULL_ADDER as per @whitequarkEddie Hung2019-07-157-8/+8
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| * ice40_opt to $__ICE40_CARRY_LUT4 into $lut not SB_LUTEddie Hung2019-07-131-9/+7
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| * Do not double count cells in abcEddie Hung2019-07-121-2/+2
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| * Use Const::from_string() not its constructor...Eddie Hung2019-07-121-1/+1
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| * Off by oneEddie Hung2019-07-121-1/+1
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| * Fix spacingEddie Hung2019-07-121-1/+1
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| * Remove double pushEddie Hung2019-07-121-1/+0
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| * Map to and from this box if -abc9Eddie Hung2019-07-121-2/+3
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| * ice40_opt to handle this box and opt back to SB_LUT4Eddie Hung2019-07-121-0/+48
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| * Add new box to cells_sim.vEddie Hung2019-07-121-2/+25
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| * _ABC macro will map and unmap to this new boxEddie Hung2019-07-122-0/+34
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| * Combine SB_CARRY+SB_LUT into one $__ICE40_CARRY_LUT4 boxEddie Hung2019-07-123-25/+13
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* | Merge pull request #1200 from mmicko/fix_typo_liberty_ccClifford Wolf2019-07-161-1/+1
|\ \ | | | | | | Fix typo, double "of"
| * | Fix typo, double "of"Miodrag Milanovic2019-07-161-1/+1
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* | | Merge pull request #1199 from mmicko/extract_fa_fixClifford Wolf2019-07-161-2/+2
|\ \ \ | |/ / |/| | Fix check logic in extract_fa
| * | Fix check logic in extract_faMiodrag Milanovic2019-07-161-2/+2
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* | Merge pull request #1196 from YosysHQ/eddie/fix1178Eddie Hung2019-07-151-5/+12
|\ \ | | | | | | Fix different synth results between with and without debug output "-g"
| * | Revert "Add log_checkpoint function and use it in opt_muxtree"Eddie Hung2019-07-153-9/+0
| | | | | | | | | | | | This reverts commit 0e6c83027f24cdf7082606a5631468ad28f41574.
| * | Revert "Fix first divergence in #1178"Eddie Hung2019-07-151-5/+1
| | | | | | | | | | | | This reverts commit 1122a2e0671ed00b7c03658f5012e34df12f26de.
| * | Merge branch 'master' into eddie/fix1178Eddie Hung2019-07-1526-93/+1204
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| * | | Redesign log_id_cache so that it doesn't keep IdString instances referenced, ↵Clifford Wolf2019-07-151-6/+13
| | | | | | | | | | | | | | | | | | | | | | | | fixes #1178 Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | | Add log_checkpoint function and use it in opt_muxtreeClifford Wolf2019-07-153-0/+9
| | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | | Fix first divergence in #1178Eddie Hung2019-07-091-1/+5
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* | | | Merge pull request #1189 from YosysHQ/eddie/fix1151Clifford Wolf2019-07-151-0/+4
|\ \ \ \ | | | | | | | | | | Error out if enable > dbits in memory_bram file
| * | | | Error out if enable > dbitsEddie Hung2019-07-131-0/+4
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* | | | | Merge pull request #1190 from YosysHQ/eddie/fix_1099Clifford Wolf2019-07-151-4/+8
|\ \ \ \ \ | | | | | | | | | | | | extract_fa to return nothing more gracefully
| * | | | | If ConstEval fails do not log_abort() but return gracefullyEddie Hung2019-07-131-4/+8
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* | | | | Merge pull request #1191 from whitequark/opt_lut-log_debugClifford Wolf2019-07-151-56/+38
|\ \ \ \ \ | | | | | | | | | | | | Make opt_lut less chatty
| * | | | | opt_lut: make less chatty.whitequark2019-07-131-56/+38
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* | | | | Merge pull request #1195 from Roman-Parise/masterClifford Wolf2019-07-151-1/+1
|\ \ \ \ \ | | | | | | | | | | | | Updated FreeBSD dependencies in README.md
| * | | | | Updated FreeBSD dependencies in README.mdRoman-Parise2019-07-141-1/+1
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* | | | | Merge pull request #1197 from nakengelhardt/handle-setrlimit-failClifford Wolf2019-07-151-1/+5
|\ \ \ \ \ | |/ / / / |/| | | | smt: handle failure of setrlimit syscall
| * | | | smt: handle failure of setrlimit syscallN. Engelhardt2019-07-151-1/+5
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* | | | Merge pull request #1194 from cr1901/miss-semiEddie Hung2019-07-141-2/+2
|\ \ \ \ | |/ / / |/| | | Fix missing semicolon in Windows-specific code in aigerparse.cc.
| * | | Fix missing semicolon in Windows-specific code in aigerparse.cc.William D. Jones2019-07-141-2/+2
| | | | | | | | | | | | | | | | Signed-off-by: William D. Jones <thor0505@comcast.net>
* | | | Merge pull request #1183 from whitequark/ice40-always-relutClifford Wolf2019-07-121-11/+5
|\ \ \ \ | |_|_|/ |/| | | synth_ice40: switch -relut to be always on
| * | | synth_ice40: switch -relut to be always on.whitequark2019-07-111-10/+4
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| * | | synth_ice40: fix help text typo. NFC.whitequark2019-07-111-1/+1
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* | | Merge pull request #1182 from koriakin/xc6s-bramEddie Hung2019-07-119-8/+598
|\ \ \ | | | | | | | | synth_xilinx: Initial Spartan 6 block RAM inference support.
| * | | synth_xilinx: Initial Spartan 6 block RAM inference support.Marcin Kościelnicki2019-07-119-8/+598
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* | | Merge pull request #1185 from koriakin/xc-ff-init-valsEddie Hung2019-07-112-6/+6
|\ \ \ | | | | | | | | xilinx: Fix the default values for FDPE/FDSE INIT attributes to match ISE/Vivado.
| * | | xilinx: Fix the default values for FDPE/FDSE INIT attributes to match ↵Marcin Kościelnicki2019-07-112-6/+6
| |/ / | | | | | | | | | ISE/Vivado.
* / / Enable &mfs for abc9, even if it only currently works for ice40Eddie Hung2019-07-111-1/+1
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* | Merge pull request #1172 from whitequark/write_verilog-Sa-as-qmarkClifford Wolf2019-07-111-2/+8
|\ \ | | | | | | write_verilog: write RTLIL::Sa aka - as Verilog ?
| * | write_verilog: write RTLIL::Sa aka - as Verilog ?.whitequark2019-07-091-2/+8
| | | | | | | | | | | | | | | | | | | | | Currently, the only ways (determined by grepping for regex \bSa\b) to end up with RTLIL::Sa in a netlist is by reading a Verilog constant with ? in it as a part of case, or by running certain FSM passes. Both of these cases should be round-tripped back to ? in Verilog.
* | | Merge pull request #1179 from whitequark/attrmap-procClifford Wolf2019-07-111-0/+19
|\ \ \ | | | | | | | | attrmap: also consider process, switch and case attributes
| * | | attrmap: also consider process, switch and case attributes.whitequark2019-07-101-0/+19
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* | | Merge pull request #1180 from YosysHQ/eddie/no_abc9_retimeEddie Hung2019-07-103-6/+15
|\ \ \ | | | | | | | | Error out if -abc9 and -retime specified
| * | | Error out if -abc9 and -retime specifiedEddie Hung2019-07-103-6/+15
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