| Commit message (Collapse) | Author | Age | Files | Lines | ||
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| * | | Be more conservative with printing decimal numbers in verilog backend | Clifford Wolf | 2014-08-02 | 1 | -2/+3 | |
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| * | | Improved verilog output for ordinary $mux cells | Clifford Wolf | 2014-08-02 | 1 | -3/+19 | |
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| * | | Bugfix in "techmap -extern" | Clifford Wolf | 2014-08-02 | 2 | -10/+17 | |
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| * | | Removed at() method from RTLIL::IdString | Clifford Wolf | 2014-08-02 | 3 | -8/+7 | |
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| * | | No implicit conversion from IdString to anything else | Clifford Wolf | 2014-08-02 | 16 | -37/+37 | |
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| * | | More bugfixes related to new RTLIL::IdString | Clifford Wolf | 2014-08-02 | 10 | -44/+60 | |
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| * | | Limit size of log_signal buffer to 100 elements | Clifford Wolf | 2014-08-02 | 2 | -2/+9 | |
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| * | | Improvements in new RTLIL::IdString implementation | Clifford Wolf | 2014-08-02 | 5 | -33/+65 | |
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| * | | Fixed a performance bug in opt_reduce | Clifford Wolf | 2014-08-02 | 1 | -2/+6 | |
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| * | | Implemented new reference counting RTLIL::IdString | Clifford Wolf | 2014-08-02 | 2 | -15/+90 | |
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| * | | Fixed memory corruption related to id2cstr() | Clifford Wolf | 2014-08-02 | 1 | -2/+2 | |
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| * | | More cleanups related to RTLIL::IdString usage | Clifford Wolf | 2014-08-02 | 33 | -261/+237 | |
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| * | | Preparations for RTLIL::IdString redesign: cleanup of existing code | Clifford Wolf | 2014-08-02 | 12 | -32/+71 | |
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| * | | Added logfile hash to statistics footer | Clifford Wolf | 2014-08-01 | 5 | -45/+79 | |
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| * | | Replaced sha1 implementation | Clifford Wolf | 2014-08-01 | 8 | -283/+334 | |
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| * | | Added per-pass cpu usage statistics | Clifford Wolf | 2014-08-01 | 4 | -12/+86 | |
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| * | | Added ModIndex helper class, some changes to RTLIL::Monitor | Clifford Wolf | 2014-08-01 | 9 | -30/+170 | |
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| * | | Packed SigBit::data and SigBit::offset in a union | Clifford Wolf | 2014-08-01 | 2 | -10/+14 | |
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| * | | Consolidated hana test benches into fewer files | Clifford Wolf | 2014-08-01 | 175 | -1332/+1622 | |
| | | | | | | | | | | | | | | | | | for pf in test_simulation_{always,and,buffer,decoder,inc,mux,nand,nor,or,seq,shifter,sop,techmap,xnor,xor}; do gawk 'FNR == 1 { printf("\n// %s\n",FILENAME); } { gsub("^module *", sprintf("module f%d_",ARGIND)); print; }' \ ${pf}_*_test.v > $pf.v; ../tools/autotest.sh $pf.v; mv -v ${pf}_*_test.v Attic/; done; ..etc.. | |||||
| * | | Added "test_autotb -n <num_iter>" option | Clifford Wolf | 2014-08-01 | 2 | -11/+32 | |
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| * | | Renamed modwalker.h to modtools.h | Clifford Wolf | 2014-07-31 | 3 | -12/+14 | |
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| * | | Various cleanups in Makefile, Renamed default configurations | Clifford Wolf | 2014-07-31 | 1 | -21/+12 | |
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| * | | Added compiler + compiler version + compiler flags to version string | Clifford Wolf | 2014-07-31 | 1 | -1/+2 | |
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| * | | Fixed build of verific bindings | Clifford Wolf | 2014-07-31 | 1 | -11/+11 | |
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| * | | Renamed port access function on RTLIL::Cell, added param access functions | Clifford Wolf | 2014-07-31 | 46 | -1059/+1086 | |
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| * | | Added "trace" command | Clifford Wolf | 2014-07-31 | 4 | -2/+103 | |
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| * | | Added RTLIL::Monitor | Clifford Wolf | 2014-07-31 | 2 | -96/+97 | |
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| * | | Added module->design and cell->module, wire->module pointers | Clifford Wolf | 2014-07-31 | 15 | -44/+142 | |
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| * | | Moved some stuff to kernel/yosys.{h,cc}, using Yosys:: namespace | Clifford Wolf | 2014-07-31 | 41 | -665/+790 | |
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| * | | Renamed "stdcells.v" to "techmap.v" | Clifford Wolf | 2014-07-31 | 9 | -12/+15 | |
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| * | | Added "techmap -assert" | Clifford Wolf | 2014-07-31 | 2 | -14/+43 | |
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| * | | Reorganized stdcells.v (no actual code change, just moved and indented stuff) | Clifford Wolf | 2014-07-31 | 1 | -747/+590 | |
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| * | | Added "yosys -A" | Clifford Wolf | 2014-07-31 | 1 | -1/+10 | |
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| * | | Added "yosys -Q" | Clifford Wolf | 2014-07-31 | 1 | -26/+35 | |
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| * | | Added techmap CONSTMAP feature | Clifford Wolf | 2014-07-30 | 3 | -12/+126 | |
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| * | | Fixed counting verilog line numbers for "// synopsys translate_off" sections | Clifford Wolf | 2014-07-30 | 2 | -4/+4 | |
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| * | | Added write_file command | Clifford Wolf | 2014-07-30 | 4 | -5/+84 | |
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| * | | Added "make -j{N}" support to "make test" | Clifford Wolf | 2014-07-30 | 7 | -22/+39 | |
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| * | | Improvements in test_cell | Clifford Wolf | 2014-07-30 | 1 | -35/+89 | |
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| * | | New techmap default rules for $shr $sshr $shl $sshl | Clifford Wolf | 2014-07-30 | 1 | -282/+62 | |
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| * | | Using native ezSAT shift ops in satgen, fixed $shift and $shiftx SAT models | Clifford Wolf | 2014-07-30 | 1 | -36/+39 | |
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| * | | Added native support for shift operations to ezSAT | Clifford Wolf | 2014-07-30 | 2 | -1/+95 | |
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| * | | Added "log_dump_val_worker(char *v)" | Clifford Wolf | 2014-07-30 | 1 | -0/+1 | |
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| * | | Added CodingStyle document | Clifford Wolf | 2014-07-30 | 1 | -0/+43 | |
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| * | | Added "kernel/yosys.h" and "kernel/yosys.cc" | Clifford Wolf | 2014-07-30 | 8 | -61/+133 | |
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| * | | Added "test_cell" command | Clifford Wolf | 2014-07-29 | 3 | -1/+186 | |
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| * | | Renamed "write_autotest" to "test_autotb" and moved to passes/tests/ | Clifford Wolf | 2014-07-29 | 5 | -10/+12 | |
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| * | | Fixed Verilog pre-processor for files with no trailing newline | Clifford Wolf | 2014-07-29 | 1 | -1/+1 | |
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| * | | Bugfix in simlib.v for iverilog | Clifford Wolf | 2014-07-29 | 1 | -5/+6 | |
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| * | | Allow "hierarchy -generate" for $__ cells | Clifford Wolf | 2014-07-29 | 1 | -1/+3 | |
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index : iCE40/yosys | |
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