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| * | | | | | | | | | | | | | | | | | | | | | | | | | | Add cells.lut to techlibs/xilinx/Eddie Hung2019-04-092-0/+16
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| * | | | | | | | | | | | | | | | | | | | | | | | | | | synth_xilinx to call abc with -lut +/xilinx/cells.lutEddie Hung2019-04-091-2/+2
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| * | | | | | | | | | | | | | | | | | | | | | | | | | | Add delays to cells.boxEddie Hung2019-04-091-4/+12
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| * | | | | | | | | | | | | | | | | | | | | | | | | | | Add "-lut <file>" support to abc9Eddie Hung2019-04-091-13/+31
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| * | | | | | | | | | | | | | | | | | | | | | | | | | | synth_xilinx with abc9 to use -boxEddie Hung2019-04-091-1/+4
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| * | | | | | | | | | | | | | | | | | | | | | | | | | | Add techlibs/xilinx/cells.boxEddie Hung2019-04-092-0/+6
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| * | | | | | | | | | | | | | | | | | | | | | | | | | | Add "-box" option to abc9Eddie Hung2019-04-091-7/+22
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| * | | | | | | | | | | | | | | | | | | | | | | | | | | Add 'setundef -zero' call prior to aigmap in abc9Eddie Hung2019-04-091-0/+4
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| * | | | | | | | | | | | | | | | | | | | | | | | | | | Comment outEddie Hung2019-04-091-1/+1
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| * | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for synth_xilinx -abc9 and ignore abc9 -dress optEddie Hung2019-04-092-1/+14
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* | | | | | | | | | | | | | | | | | | | | | | | | | | | Merge remote-tracking branch 'origin/master' into xaigEddie Hung2019-06-12140-1863/+4709
|\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ | |_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|/ / / / / / / / |/| | | | | | | | | | | | | | | | | | | | | | | | | / / | | |_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|/ / | |/| | | | | | | | | | | | | | | | | | | | | | | | |
| * | | | | | | | | | | | | | | | | | | | | | | | | | Add some more commentsEddie Hung2019-06-101-1/+6
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| * | | | | | | | | | | | | | | | | | | | | | | | | | Merge pull request #1082 from corecode/u4kDavid Shah2019-06-101-0/+24
| |\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | ice40/cells_sim.v: Add support for RGB_DRV/LED_DRV_CUR for u4k
| | * | | | | | | | | | | | | | | | | | | | | | | | | | ice40/cells_sim.v: Add support for RGB_DRV/LED_DRV_CUR for u4kSimon Schubert2019-06-101-0/+24
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| * | | | | | | | | | | | | | | | | | | | | | | | | | Merge pull request #1078 from YosysHQ/eddie/muxcover_costsClifford Wolf2019-06-081-12/+42
| |\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ | | |_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|/ / | |/| | | | | | | | | | | | | | | | | | | | | | | | | Allow muxcover costs to be changed
| | * | | | | | | | | | | | | | | | | | | | | | | | | Allow muxcover costs to be changedEddie Hung2019-06-071-12/+42
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| * | | | | | | | | | | | | | | | | | | | | | | | | Fix spacing from spaces to tabsEddie Hung2019-06-071-362/+362
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| * | | | | | | | | | | | | | | | | | | | | | | | | Merge pull request #1079 from YosysHQ/eddie/fix_read_aigerClifford Wolf2019-06-0727-45/+128
| |\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix read_aiger to really get tested, and fix some uncovered read_aiger issues
| | * | | | | | | | | | | | | | | | | | | | | | | | | Add read_aiger to CHANGELOGEddie Hung2019-06-071-0/+1
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| | * | | | | | | | | | | | | | | | | | | | | | | | | Fix spacing (entire file is wrong anyway, will fix later)Eddie Hung2019-06-071-3/+3
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| | * | | | | | | | | | | | | | | | | | | | | | | | | Remove unnecessary std::getline() for ASCIIEddie Hung2019-06-071-3/+0
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| | * | | | | | | | | | | | | | | | | | | | | | | | | Test *.aag too, by using *.aig as referenceEddie Hung2019-06-071-0/+19
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| | * | | | | | | | | | | | | | | | | | | | | | | | | Fix read_aiger -- create zero driver, fix init width, parse 'b'Eddie Hung2019-06-072-13/+52
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| | * | | | | | | | | | | | | | | | | | | | | | | | | Use ABC to convert from AIGER to VerilogEddie Hung2019-06-071-2/+3
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| | * | | | | | | | | | | | | | | | | | | | | | | | | Use ABC to convert AIGER to Verilog, then sat against YosysEddie Hung2019-06-071-21/+15
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| | * | | | | | | | | | | | | | | | | | | | | | | | | Add symbols to AIGER test inputs for ABCEddie Hung2019-06-0722-8/+40
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| * | | | | | | | | | | | | | | | | | | | | | | | | Merge pull request #1077 from YosysHQ/clifford/pr983Clifford Wolf2019-06-079-3/+93
| |\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | elaboration system tasks
| | * | | | | | | | | | | | | | | | | | | | | | | | | Fixes and cleanups in AST_TECALL handlingClifford Wolf2019-06-074-50/+38
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| | * | | | | | | | | | | | | | | | | | | | | | | | | Merge branch 'pr_elab_sys_tasks' of https://github.com/udif/yosys into ↵Clifford Wolf2019-06-0710-5/+107
| | |\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | clifford/pr983
| | | * | | | | | | | | | | | | | | | | | | | | | | | | Initial implementation of elaboration system tasksUdi Finkelstein2019-05-0310-5/+107
| | | | |_|_|_|_|_|_|_|_|_|_|_|_|/ / / / / / / / / / / | | | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | (IEEE1800-2017 section 20.11) This PR allows us to use $info/$warning/$error/$fatal **at elaboration time** within a generate block. This is very useful to stop a synthesis of a parametrized block when an illegal combination of parameters is chosen.
| * | / | | | | | | | | | | | | | | | | | | | | | | | Rename implicit_ports.sv test to implicit_ports.vClifford Wolf2019-06-071-0/+0
| |/ / / / / / / / / / / / / / / / / / / / / / / / / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | | | | | | | | | | | | | | | | | | | | | | | | Merge branch 'tux3-implicit_named_connection'Clifford Wolf2019-06-074-3/+40
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| | * | | | | | | | | | | | | | | | | | | | | | | | | Cleanup tux3-implicit_named_connectionClifford Wolf2019-06-073-13/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| | * | | | | | | | | | | | | | | | | | | | | | | | | Merge branch 'implicit_named_connection' of https://github.com/tux3/yosys ↵Clifford Wolf2019-06-075-4/+52
| | |\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ | | | |_|/ / / / / / / / / / / / / / / / / / / / / / / | | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | into tux3-implicit_named_connection
| | | * | | | | | | | | | | | | | | | | | | | | | | | SystemVerilog support for implicit named port connectionstux32019-06-065-12/+59
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is the `foo foo(.port1, .port2);` SystemVerilog syntax introduced in IEEE1800-2005.
| * | | | | | | | | | | | | | | | | | | | | | | | | | Merge pull request #1076 from thasti/centos7-build-fixClifford Wolf2019-06-071-1/+0
| |\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ | | |/ / / / / / / / / / / / / / / / / / / / / / / / / | |/| | | | | | | | | | | | | | | | | | | | | | | | | Fix pyosys-build on CentOS7
| | * | | | | | | | | | | | | | | | | | | | | | | | | remove boost/log/exceptions.hpp from wrapper generatorStefan Biereigel2019-06-071-1/+0
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| * | | | | | | | | | | | | | | | | | | | | | | | | Merge pull request #1060 from antmicro/parsing_attr_on_port_connClifford Wolf2019-06-0614-10/+279
| |\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Added support for parsing attributes on port connections.
| | * | | | | | | | | | | | | | | | | | | | | | | | | Fixed memory leak.Maciej Kurc2019-06-051-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
| | * | | | | | | | | | | | | | | | | | | | | | | | | Moved tests that fail with Icarus Verilog to /tests/various. Those tests are ↵Maciej Kurc2019-06-044-0/+46
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | just for parsing Verilog. Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
| | * | | | | | | | | | | | | | | | | | | | | | | | | Added tests for attributesMaciej Kurc2019-06-039-0/+219
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
| | * | | | | | | | | | | | | | | | | | | | | | | | | Added support for parsing attributes on port connections.Maciej Kurc2019-05-311-10/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
| * | | | | | | | | | | | | | | | | | | | | | | | | | Merge pull request #1073 from whitequark/ecp5-diamond-iobDavid Shah2019-06-061-0/+15
| |\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | ECP5: implement most Diamond I/O buffer primitives
| | * | | | | | | | | | | | | | | | | | | | | | | | | | ECP5: implement all Diamond I/O buffer primitives.whitequark2019-06-061-0/+15
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| * | | | | | | | | | | | | | | | | | | | | | | | | | | Merge pull request #1071 from YosysHQ/eddie/fix_1070Clifford Wolf2019-06-061-2/+2
| |\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix typo in opt_rmdff causing register to be incorrectly removed
| | * | | | | | | | | | | | | | | | | | | | | | | | | | | Fix typo in opt_rmdffEddie Hung2019-06-051-2/+2
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| * | | | | | | | | | | | | | | | | | | | | | | | | | | | Merge pull request #1072 from YosysHQ/eddie/fix_1069Clifford Wolf2019-06-061-0/+5
| |\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Error out if no top module given before 'sim'
| | * | | | | | | | | | | | | | | | | | | | | | | | | | | | Error out if no top module given before 'sim'Eddie Hung2019-06-051-0/+5
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| * / / / / / / / / / / / / / / / / / / / / / / / / / / / Missing doc for -tech xilinx in shregmapEddie Hung2019-06-051-0/+3
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| * | | | | | | | | | | | | | | | | | | | | | | | | | | Merge pull request #1067 from YosysHQ/clifford/fix1065Eddie Hung2019-06-051-1/+1
| |\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ | | | |_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|/ / / | | |/| | | | | | | | | | | | | | | | | | | | | | | / / | | |_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|/ / | |/| | | | | | | | | | | | | | | | | | | | | | | | | Suppress driver-driver conflict warning for unknown cell types
generated by cgit v1.2.3 (git 2.25.1) at 2025-08-03 07:24:02 +0000