| Commit message (Collapse) | Author | Age | Files | Lines | ||
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| * | Added -S option for simple synthesis to gate logic | Clifford Wolf | 2013-03-21 | 1 | -2/+17 | |
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| * | Avoid verilog-2k in verilog backend | Clifford Wolf | 2013-03-21 | 1 | -0/+17 | |
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| * | Disabled the per-default dumping of ILANG code | Clifford Wolf | 2013-03-21 | 1 | -1/+6 | |
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| * | Added -nomap option to memory pass | Clifford Wolf | 2013-03-21 | 1 | -5/+19 | |
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| * | Merge branch 'hansiglaser-master' | Clifford Wolf | 2013-03-19 | 3 | -10/+57 | |
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| | * | added optimizations for single-bit $eq/$ne with constant input to opt_const | Clifford Wolf | 2013-03-19 | 1 | -0/+25 | |
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| | * | improved $mux optimization in opt_const | Clifford Wolf | 2013-03-19 | 1 | -2/+6 | |
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| | * | keep $mux and $_MUX_ optimizations separate in opt_const | Clifford Wolf | 2013-03-19 | 1 | -3/+3 | |
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| | * | added a TODO | Johann Glaser | 2013-03-18 | 1 | -0/+2 | |
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| | * | added one more suggestion to optimize MUXes in pass "opt_const" | Johann Glaser | 2013-03-18 | 1 | -0/+1 | |
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| | * | also optimize single-bit "$mux" cells in pass "opt_const", added suggestions | Johann Glaser | 2013-03-18 | 1 | -1/+5 | |
| | | | | | | | | | for more optimizations | |||||
| | * | fixed a crash when lines start with whitespace | Johann Glaser | 2013-03-18 | 1 | -2/+2 | |
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| | * | added description of Makefile include files for build configuration | Johann Glaser | 2013-03-18 | 1 | -6/+17 | |
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| * | More TODOs in README | Clifford Wolf | 2013-03-18 | 1 | -1/+7 | |
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| * | Merge branch 'hansi' | Clifford Wolf | 2013-03-18 | 13 | -29/+30 | |
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| | * | Removed date from auto-generated passes/techmap/stdcells.inc | Clifford Wolf | 2013-03-18 | 1 | -2/+1 | |
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| | * | Fixed abc eeror handling | Clifford Wolf | 2013-03-18 | 1 | -2/+2 | |
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| | * | add header to autogenerated file on its origin | Johann Glaser | 2013-03-18 | 1 | -1/+3 | |
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| | * | fixed typos | Johann Glaser | 2013-03-18 | 12 | -26/+26 | |
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| * | Fixed strerrno vs. strerror types in ABC pass | Clifford Wolf | 2013-03-17 | 1 | -4/+4 | |
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| * | Merge branch 'hansi' | Clifford Wolf | 2013-03-17 | 5 | -22/+49 | |
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| | * | Cleaned up ABC file/io error handling | Clifford Wolf | 2013-03-17 | 1 | -15/+13 | |
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| | * | Set execute bit on tests/openmsp430/run-synth.sh for real | Clifford Wolf | 2013-03-17 | 1 | -0/+0 | |
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| | * | added error checking at execution of ABC | Johann Glaser | 2013-03-17 | 1 | -1/+19 | |
| | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| | * | corrected typos | Johann Glaser | 2013-03-17 | 1 | -2/+2 | |
| | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| | * | set executable flags to run-synth.sh, added .gitignore | Johann Glaser | 2013-03-17 | 1 | -0/+3 | |
| | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| | * | added ckeck for Icarus Verilog, otherwise the tests are silently stopped | Johann Glaser | 2013-03-17 | 1 | -0/+7 | |
| | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| | * | corrected typos | Johann Glaser | 2013-03-17 | 1 | -16/+17 | |
| |/ | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | Fixed gcc warnings and added error handling to shell escape | Clifford Wolf | 2013-03-15 | 2 | -1/+5 | |
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| * | Added scc pass (find logic loops) | Clifford Wolf | 2013-03-15 | 2 | -0/+300 | |
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| * | Added vi .*.swp files to .gitignore | Clifford Wolf | 2013-03-15 | 1 | -0/+1 | |
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| * | Added [[CITE]] tags to abc and fsm_extract passes | Clifford Wolf | 2013-03-15 | 2 | -1/+15 | |
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| * | Added additional functionality and cleanups in sigtools.h and celltypes.h | Clifford Wolf | 2013-03-15 | 2 | -0/+33 | |
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| * | Changed prefix for selection operators from # to % | Clifford Wolf | 2013-03-14 | 1 | -28/+28 | |
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| * | Added #ci and #co selection operators | Clifford Wolf | 2013-03-14 | 2 | -90/+136 | |
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| * | Added more features to #x selection operator | Clifford Wolf | 2013-03-14 | 1 | -18/+42 | |
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| * | Added "select -write" command | Clifford Wolf | 2013-03-14 | 1 | -7/+23 | |
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| * | More support code for $sr cells | Clifford Wolf | 2013-03-14 | 2 | -1/+50 | |
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| * | Added $sr cell type to celltypes.h | Clifford Wolf | 2013-03-14 | 1 | -0/+1 | |
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| * | Fixed detection of public wires in opt_rmunused | Clifford Wolf | 2013-03-10 | 1 | -3/+3 | |
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| * | Added shell escape to command language | Clifford Wolf | 2013-03-10 | 1 | -0/+13 | |
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| * | Fixed and improved #x selection operator | Clifford Wolf | 2013-03-08 | 1 | -14/+44 | |
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| * | Automatically select new objects in abc and techmap passes | Clifford Wolf | 2013-03-08 | 3 | -1/+19 | |
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| * | Added ## selection operator (union all on stack) | Clifford Wolf | 2013-03-08 | 1 | -0/+9 | |
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| * | Added select -count mode | Clifford Wolf | 2013-03-08 | 1 | -11/+24 | |
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| * | Split extract -attr into extract -cell_attr and -wire_attr | Clifford Wolf | 2013-03-08 | 1 | -28/+35 | |
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| * | Added support for attribute matching in extract pass | Clifford Wolf | 2013-03-07 | 1 | -1/+60 | |
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| * | Added portmapping support to subcircuit userCompareNodes() api | Clifford Wolf | 2013-03-07 | 2 | -23/+29 | |
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| * | Cleanups and improvements in Makefile | Clifford Wolf | 2013-03-07 | 1 | -2/+17 | |
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| * | Fixed parsing of select #x<num> operator | Clifford Wolf | 2013-03-06 | 1 | -0/+1 | |
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index : iCE40/yosys | |
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