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* Merge pull request #2973 from YosysHQ/micko/optional_extensionsMiodrag Milanović2021-08-202-2/+12
|\ | | | | Make Verific extensions optional
| * Make Verific extensions optionalMiodrag Milanovic2021-08-202-2/+12
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* Bump versiongithub-actions[bot]2021-08-181-1/+1
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* ice40: Fix typo in SB_CARRY specify for LP/UltraPlusSylvain Munaut2021-08-171-2/+2
| | | | Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
* Bump versiongithub-actions[bot]2021-08-171-1/+1
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* kernel/mem: Remove old parameter when upgrading $mem to $mem_v2.Marcelina Kościelnicka2021-08-161-0/+1
| | | | Fixes #2967.
* Bump versiongithub-actions[bot]2021-08-151-1/+1
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* proc_prune: Make assign removal and promotion per-bit, remember promoted bits.Marcelina Kościelnicka2021-08-142-40/+47
| | | | Fixes #2962.
* Bump versiongithub-actions[bot]2021-08-141-1/+1
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* Generate an RTLIL representation of bind constructsRupert Swarbrick2021-08-1311-3/+312
| | | | | | | | | | | | | | | | | | | | | | | | | This code now takes the AST nodes of type AST_BIND and generates a representation in the RTLIL for them. This is a little tricky, because a binding of the form: bind baz foo_t foo_i (.arg (1 + bar)); means "make an instance of foo_t called foo_i, instantiate it inside baz and connect the port arg to the result of the expression 1+bar". Of course, 1+bar needs a cell for the addition. Where should that cell live? With this patch, the Binding structure that represents the construct is itself an AST::AstModule module. This lets us put the adder cell inside it. We'll pull the contents out and plonk them into 'baz' when we actually do the binding operation as part of the hierarchy pass. Of course, we don't want RTLIL::Binding to contain an AST::AstModule (since kernel code shouldn't depend on a frontend), so we define RTLIL::Binding as an abstract base class and put the AST-specific code into an AST::Binding subclass. This is analogous to the AST::AstModule class.
* Add opt_mem_widen pass.Marcelina Kościelnicka2021-08-144-0/+146
| | | | If all of us are wide, then none of us are!
* memory_share: Add -nosat and -nowiden options.Marcelina Kościelnicka2021-08-1411-11/+269
| | | | This unlocks wide port recognition by default.
* memory_dff: Recognize soft transparency logic.Marcelina Kościelnicka2021-08-134-7/+1355
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* Add new opt_mem_priority pass.Marcelina Kościelnicka2021-08-134-2/+319
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* Merge pull request #2932 from YosysHQ/mwk/logger-check-expectedMiodrag Milanović2021-08-132-5/+14
|\ | | | | logger: Add -check-expected subcommand.
| * logger: Add -check-expected subcommand.Marcelina Kościelnicka2021-08-122-5/+14
| | | | | | | | | | This allows us to have multiple "expect this warning" calls in a single long script, covering only as many passes as necessary.
* | sv: improve support for wire and var with user-defined typesBrett Witherspoon2021-08-123-11/+152
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - User-defined types must be data types. Using a net type (e.g. wire) is a syntax error. - User-defined types without a net type are always variables (i.e. logic). - Nets and variables can now be explicitly declared using user-defined types: typedef logic [1:0] W; wire W w; typedef logic [1:0] V; var V v; Fixes #2846
* | Bump versiongithub-actions[bot]2021-08-131-1/+1
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* | memory_share: Pass addresses through sigmap_xmux everywhere.Marcelina Kościelnicka2021-08-131-20/+25
|/ | | | This fixes wide port recognition in some cases.
* Bump versiongithub-actions[bot]2021-08-121-1/+1
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* test/arch/{ecp5,ice40}/memories.ys: Use read_verilog -defer.Marcelina Kościelnicka2021-08-112-78/+156
| | | | | | | | | | These parts keep rereading a Verilog module, then using chparam to test it with various parameter combinations. Since the default parameters are on the large side, this spends a lot of time needlessly elaborating the default parametrization that will then be discarded. Fix it with -deref and manual hierarchy call. Shaves 30s off the test time on my machine.
* memory_dff: Recognize read ports with reset / initial value.Marcelina Kościelnicka2021-08-114-8/+55
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* proc_memwr: Use the v2 memwr cell.Marcelina Kościelnicka2021-08-113-14/+24
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* Add v2 memory cells.Marcelina Kościelnicka2021-08-1122-206/+631
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* Bump versiongithub-actions[bot]2021-08-111-1/+1
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* kernel/mem: Introduce transparency masks.Marcelina Kościelnicka2021-08-118-118/+408
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* Allow optional comma after last entry in enumMichael Singer2021-08-091-11/+12
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* Bump versiongithub-actions[bot]2021-08-101-1/+1
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* Refactor common parts of SAT-using optimizations into a helper.Marcelina Kościelnicka2021-08-097-153/+224
| | | | | | | | | | | | | This also aligns the functionality: - in all cases, the onehot attribute is used to create appropriate constraints (previously, opt_dff didn't do it at all, and share created one-hot constraints based on $pmux presence alone, which is unsound) - in all cases, shift and mul/div/pow cells are now skipped when importing the SAT problem (previously only memory_share did this) — this avoids creating clauses for hard cells that are unlikely to help with proving the UNSATness needed for optimization
* Bump versiongithub-actions[bot]2021-08-081-1/+1
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* opt_merge: Use FfInitVals.Marcelina Kościelnicka2021-08-083-28/+51
| | | | Partial #2920 fix.
* Bump versiongithub-actions[bot]2021-08-071-1/+1
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* verilog: Support tri/triand/trior wire types.Marcelina Kościelnicka2021-08-061-0/+3
| | | | | | These are, by the standard, just aliases for wire/wand/wor. Fixes #2918.
* Bump versiongithub-actions[bot]2021-08-051-1/+1
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* memory_share: Don't skip ports with EN wired to input for SAT sharing.Marcelina Kościelnicka2021-08-041-3/+1
| | | | Fixes #2912.
* Bump versiongithub-actions[bot]2021-08-041-1/+1
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* memory_bram: Move init data swizzling before other swizzling.Marcelina Kościelnicka2021-08-031-18/+18
| | | | Fixes #2907.
* Bump versiongithub-actions[bot]2021-08-031-1/+1
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* Require latest verificMiodrag Milanovic2021-08-021-1/+1
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* Bump versiongithub-actions[bot]2021-08-021-1/+1
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* backend/verilog: Add alternate mode for transparent read port output.Marcelina Kościelnicka2021-08-011-1/+71
| | | | | | This mode will be used whenever read port cannot be handled in the "extract address register" way, ie. whenever it has enable, reset, init functionality or (in the future) mixed transparency mask.
* memory_bram: Some refactoringMarcelina Kościelnicka2021-08-011-196/+174
| | | | | | This will make more sense when the new transparency masks land. Fixes #2902.
* Bump versiongithub-actions[bot]2021-07-311-1/+1
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* Update version.ymlMiodrag Milanović2021-07-301-2/+5
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* Fixes xc7 BRAM36sMaciej Dudek2021-07-301-4/+6
| | | | | | UG473 from Xilinx states that 15 bit should always be set if RAMB isn't in cascade mode. Signed-off-by: Maciej Dudek <mdudek@antmicro.com>
* proc_rmdead: use explicit pattern set when there are no wildcardsZachary Snow2021-07-294-2/+386
| | | | | | | | If width of a case expression was large, explicit patterns could cause the existing logic to take an extremely long time, or exhaust the maximum size of the underlying set. For cases where all of the patterns are fully defined and there are no constants in the case expression, this change uses a simple set to track which patterns have been seen.
* genrtlil: add width detection for AST_PREFIX nodesZachary Snow2021-07-292-0/+26
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* Bump versiongithub-actions[bot]2021-07-301-1/+1
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* opt_lut: Allow more than one -dlogic per cell type.Marcelina Kościelnicka2021-07-293-24/+55
| | | | Fixes #2061.
* verilog: save and restore overwritten macro argumentsZachary Snow2021-07-284-4/+54
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