| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | Bump version | Yosys Bot | 2020-12-09 | 1 | -1/+1 |
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| * | Merge pull request #2478 from whitequark/improve-bugpoint | whitequark | 2020-12-08 | 2 | -19/+101 |
| |\ | | | | | bugpoint: various improvements | ||||
| | * | bugpoint: add -wires option. | whitequark | 2020-12-07 | 2 | -4/+39 |
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| | * | bugpoint: try to remove whole processes first. | whitequark | 2020-12-07 | 1 | -4/+40 |
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| | * | bugpoint: accept quoted strings in -grep. | whitequark | 2020-12-07 | 1 | -1/+4 |
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| | * | bugpoint: add -command option. | whitequark | 2020-12-07 | 1 | -13/+21 |
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| * | Bump version | Yosys Bot | 2020-12-04 | 1 | -1/+1 |
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| * | Merge pull request #2470 from whitequark/cxxrtl-create_at | whitequark | 2020-12-03 | 2 | -1/+20 |
| |\ | | | | | cxxrtl: allow customizing the root module path in the C API | ||||
| | * | cxxrtl: allow customizing the root module path in the C API. | whitequark | 2020-12-03 | 2 | -1/+20 |
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| * | Bump version | Yosys Bot | 2020-12-03 | 1 | -1/+1 |
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| * | Merge pull request #2468 from whitequark/cxxrtl-assert | whitequark | 2020-12-02 | 2 | -2/+16 |
| |\ | | | | | cxxrtl: use CXXRTL_ASSERT for RTL contract violations instead of assert | ||||
| | * | cxxrtl: use CXXRTL_ASSERT for RTL contract violations instead of assert. | whitequark | 2020-12-02 | 2 | -2/+16 |
| | | | | | | | | | | | | | | | | | RTL contract violations and C++ contract violations are different: the former depend on the netlist and will never violate memory safety whereas the latter may. When loading a CXXRTL simulation into another process, RTL contract violations should generally not crash it, while C++ contract violations should. | ||||
| * | | Merge pull request #2469 from whitequark/cxxrtl-no-clk | whitequark | 2020-12-02 | 1 | -6/+14 |
| |\ \ | | | | | | | cxxrtl: fix crashes caused by a floating or constant clock input | ||||
| | * | | cxxrtl: fix crashes caused by a floating or constant clock input. | whitequark | 2020-12-02 | 1 | -6/+14 |
| | |/ | | | | | | | | | | | | | | | | | | | | | E.g. in: module test; wire clk = 0; reg data; always @(posedge clk) data <= 0; endmodule | ||||
| * | | Merge pull request #2466 from whitequark/cxxrtl-reset | whitequark | 2020-12-02 | 4 | -3/+78 |
| |\ \ | | | | | | | cxxrtl: provide a way to perform unobtrusive power-on reset | ||||
| | * | | cxxrtl: provide a way to perform unobtrusive power-on reset. | whitequark | 2020-12-02 | 4 | -3/+78 |
| | |/ | | | | | | | | | | | | | | | | | | | | | Although it is always possible to destroy and recreate the design to simulate a power-on reset, this has two drawbacks: * Black boxes are also destroyed and recreated, which causes them to reacquire their resources, which might be costly and/or erase important state. * Pointers into the design are invalidated and have to be acquired again, which is costly and might be very inconvenient if they are captured elsewhere (especially through the C API). | ||||
| * | | Merge pull request #2456 from Zottel/master | whitequark | 2020-12-02 | 1 | -0/+1 |
| |\ \ | | | | | | | Return correct modname when found in cache. | ||||
| | * | | Return correct modname when found in cache. | Julius Roob | 2020-11-26 | 1 | -0/+1 |
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| * | | | Merge pull request #2455 from gsomlo/gls-fedpkg-fixes | whitequark | 2020-12-02 | 2 | -0/+6 |
| |\ \ \ | | | | | | | | | Fixes for building Fedora distro RPMs of yosys | ||||
| | * | | | fixup over commit 829b5cca to re-enable ABCEXTERNAL support | Gabriel Somlo | 2020-11-26 | 1 | -0/+5 |
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| | * | | | Add #include needed to build with gcc-11 | Gabriel Somlo | 2020-11-26 | 1 | -0/+1 |
| | |/ / | | | | | | | | | | Suggested by Jeff Law <law@redhat.com> | ||||
| * | | | Merge pull request #2467 from YosysHQ/dave/nexus-carry-fix | David Shah | 2020-12-02 | 1 | -2/+2 |
| |\ \ \ | | | | | | | | | nexus: More efficient CO mapping | ||||
| | * | | | nexus: More efficient CO mapping | David Shah | 2020-12-02 | 1 | -2/+2 |
| | | | | | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me> | ||||
| * | | | | Merge pull request #2446 from RobertBaruch/rtlil_format | whitequark | 2020-12-02 | 3 | -0/+307 |
| |\ \ \ \ | | | | | | | | | | | Adds appendix on RTLIL text format | ||||
| | * | | | | Further juggles the wording of "character". | Robert Baruch | 2020-11-25 | 1 | -1/+1 |
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| | * | | | | Clarifies how character encodings work. | Robert Baruch | 2020-11-25 | 1 | -5/+5 |
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| | * | | | | Clarifies whitespace and eol. | Robert Baruch | 2020-11-25 | 1 | -2/+6 |
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| | * | | | | Cleans up doublequotes | Robert Baruch | 2020-11-25 | 1 | -2/+2 |
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| | * | | | | Clarifies use of integers, and character set. | Robert Baruch | 2020-11-25 | 1 | -4/+12 |
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| | * | | | | Clarifies processes, corrects some attributes | Robert Baruch | 2020-11-25 | 1 | -29/+46 |
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| | * | | | | Refactors for attributes. | Robert Baruch | 2020-11-24 | 1 | -50/+50 |
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| | * | | | | Cleans up some descriptions and syntax | Robert Baruch | 2020-11-24 | 1 | -25/+43 |
| | | | | | | | | | | | | | | | | Now all rules ending in "-stmt" end in eol. | ||||
| | * | | | | Adds missing "end" and eol to module. | Robert Baruch | 2020-11-22 | 1 | -1/+1 |
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| | * | | | | Update to Values #2 | Robert Baruch | 2020-11-22 | 1 | -1/+1 |
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| | * | | | | Update to Values section | Robert Baruch | 2020-11-22 | 1 | -2/+2 |
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| | * | | | | Adds appendix on RTLIL text format | Robert Baruch | 2020-11-22 | 3 | -0/+260 |
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| * | | | | | Bump required Verific version | Miodrag Milanovic | 2020-12-02 | 1 | -1/+1 |
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| * | | | | | Bump version | Yosys Bot | 2020-12-02 | 1 | -1/+1 |
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| * | | | | Merge pull request #2463 from georgerennie/fix_verilog_frontend_auto_defines | Claire Xen | 2020-12-01 | 2 | -1/+3 |
| |\ \ \ \ | |_|/ / |/| | | | Fix SYNTHESIS always being defined in Verilog frontend | ||||
| | * | | | Fix SYNTHESIS always being defined in Verilog frontend | georgerennie | 2020-12-01 | 2 | -1/+3 |
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| * | | | Merge pull request #2460 from pepijndevos/simple-gowin | Miodrag Milanović | 2020-12-01 | 1 | -3/+32 |
| |\ \ \ | |/ / |/| | | add -noalu and -json option for apicula | ||||
| | * | | add -noalu and -json option for apicula | Pepijn de Vos | 2020-11-30 | 1 | -3/+32 |
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| * | | Bump version | Yosys Bot | 2020-11-26 | 1 | -1/+1 |
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| * | | Merge pull request #2452 from whitequark/rtlil-remove-dot-identifiers | whitequark | 2020-11-25 | 1 | -1/+0 |
| |\ \ | | | | | | | rtlil: remove dotted identifiers | ||||
| | * | | rtlil: remove dotted identifiers. | whitequark | 2020-11-25 | 1 | -1/+0 |
| | | | | | | | | | | | | | No one knows where they came from and they never did anything useful. | ||||
| * | | | Merge pull request #2453 from YosysHQ/mmicko/verilog_assignments | Miodrag Milanović | 2020-11-25 | 1 | -6/+26 |
| |\ \ \ | | | | | | | | | Generate only simple assignments in verilog backend | ||||
| | * | | | Add verilog backend option for simple_lhs | Miodrag Milanovic | 2020-11-25 | 1 | -6/+22 |
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| | * | | | generate only simple assignments in verilog backend | Miodrag Milanovic | 2020-11-25 | 1 | -5/+9 |
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| * | | | Merge pull request #2133 from dh73/nodev_head | Claire Xen | 2020-11-25 | 18 | -65/+322 |
| |\ \ \ | | | | | | | | | Adding latch tests for shift&mask AST dynamic part-select enhancements | ||||
| | * | | | Removing trailing whitespace | diego | 2020-06-10 | 1 | -30/+30 |
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index : iCE40/yosys | |
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