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* Add first draft of eASIC back-endClifford Wolf2017-09-292-0/+191
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* Fix synth_ice40 doc regarding -top defaultClifford Wolf2017-09-291-1/+1
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* Allow $size and $bits in verilog mode, actually check test caseClifford Wolf2017-09-293-1/+3
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* Merge pull request #425 from udif/udif_dollar_bitsClifford Wolf2017-09-292-1/+103
|\ | | | | Add $bits() and $size()
| * $size() now works correctly for all cases!Udi Finkelstein2017-09-262-22/+28
| | | | | | | | It seems the issues was that AST_MULTIRANGE is converted into a multirange_dimensions[] array on the AST_MEMORY node directly.
| * $size() seems to work now with or without the optional parameter.Udi Finkelstein2017-09-262-18/+58
| | | | | | | | Multidimensional arrays still don't work. I suspect the problem is that the array is flattened into a 1D array before $size() is evaluated.
| * enable $bits() and $size() functions only when the SystemVerilog flag is ↵Udi Finkelstein2017-09-261-1/+1
| | | | | | | | enabled for read_verilog
| * Added $bits() for memories as well.Udi Finkelstein2017-09-262-8/+31
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| * $size() now works with memories as well!Udi Finkelstein2017-09-262-3/+7
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| * Add $size() function. At the moment it works only on expressions, not on ↵Udi Finkelstein2017-09-262-0/+29
|/ | | | memories.
* Merge pull request #421 from stephengroat/osx-travisClifford Wolf2017-09-283-2/+12
|\ | | | | Add osx tests using brew bundle
| * delete bad backslashStephen2017-09-271-1/+1
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| * forgot to install bundlesStephen2017-09-271-0/+1
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| * Add osx tests using brew bundleStephen Groat2017-09-273-2/+11
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* Increase maximum LUT size in blifparse to 12 bitsClifford Wolf2017-09-271-1/+1
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* Parse reals as string in JSON front-endClifford Wolf2017-09-261-0/+28
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* Merge branch 'vlogpp-inc-fixes'Clifford Wolf2017-09-261-41/+69
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| * Minor coding style fixClifford Wolf2017-09-261-1/+1
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| * Merge branch 'master' of https://github.com/combinatorylogic/yosys into ↵Clifford Wolf2017-09-261-41/+69
|/| | | | | | | combinatorylogic-master
| * Adding support for string macros and macros with arguments after includecombinatorylogic2017-09-211-41/+69
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* | Fix ignoring of simulation timings so that invalid module parameters cause ↵Clifford Wolf2017-09-262-4/+2
|/ | | | syntax errors
* Merge pull request #413 from azonenberg/extract-reduce-tweaksClifford Wolf2017-09-161-86/+170
|\ | | | | Added support for off-chain loads in extract_reduce
| * Added missing "break"Andrew Zonenberg2017-09-151-0/+1
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| * Implemented off-chain support for extract_reduceAndrew Zonenberg2017-09-151-84/+157
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| * extract_reduce now only removes the head of the chain, relying on "clean" to ↵Andrew Zonenberg2017-09-151-9/+19
|/ | | | delete upstream cells. Added "-allow-off-chain" flag, but it's currently ignored.
* Merge branch 'master' of github.com:cliffordwolf/yosysClifford Wolf2017-09-151-2/+2
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| * Merge pull request #412 from azonenberg/reduce-fixesClifford Wolf2017-09-141-2/+2
| |\ | | | | | | extract_reduce: Fix segfault on "undriven" inputs
| | * extract_reduce: Fix segfault on "undriven" inputsRobert Ou2017-09-141-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | This is easily triggered when un-techmapping if the technology-specific cell library isn't loaded. Outputs of technology-specific cells will be seen as inputs, and nets using those outputs will be seen as undriven. Just ignore these cells because they can't be part of a reduce chain anyways.
* | | Update ABC to hg rev cd6984ee82d4Clifford Wolf2017-09-151-2/+2
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* | Merge pull request #411 from azonenberg/counter-extraction-fixesClifford Wolf2017-09-143-68/+183
|\ \ | | | | | | Various improvements and bug fixes to extract_counter
| * | Fixed bug where counter extraction on non-GreenPAK devices incorrectly ↵Andrew Zonenberg2017-09-141-32/+27
| | | | | | | | | | | | handled parallel counter output
| * | Added support for inferring counters with reset to full scale instead of zeroAndrew Zonenberg2017-09-141-4/+11
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| * | Added RESET_TO_MAX parameter to $__COUNT_ cell. Cannot yet be extracted.Andrew Zonenberg2017-09-143-2/+5
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| * | Added support for inferring counters with active-low resetAndrew Zonenberg2017-09-141-6/+15
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| * | Initial support for extraction of counters with clock enableAndrew Zonenberg2017-09-142-30/+131
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| * | Fixed typo in comment. Fixed bug where extract_counter would create up ↵Andrew Zonenberg2017-09-141-2/+2
| |/ | | | | | | counters when it meant to create down counters.
* | Merge pull request #410 from azonenberg/opt_demorganClifford Wolf2017-09-142-1/+204
|\ \ | |/ |/| Added "opt_demorgan" pass (fixes #408)
| * Minor changes to opt_demorgan requested during code reviewAndrew Zonenberg2017-09-142-18/+18
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| * Initial version of opt_demorgan is functioning for AND/OR gates. Not the ↵Andrew Zonenberg2017-09-122-0/+203
|/ | | | prettiest results for bus inputs, but this can be improved
* Add src attribute to extra cells generated by proc_dlatchClifford Wolf2017-09-091-7/+9
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* Add src arguments to all cell creator helper functionsClifford Wolf2017-09-092-209/+244
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* Further improve extract_fa (but still buggy)Clifford Wolf2017-09-021-28/+91
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* Merge pull request #406 from azonenberg/coolrunner-techmapClifford Wolf2017-09-022-18/+125
|\ | | | | Coolrunner techmapping improvements
| * coolrunner2: Finish fixing special-use p-termsRobert Ou2017-09-011-8/+20
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| * coolrunner2: Generate a feed-through AND term when necessaryRobert Ou2017-09-011-13/+31
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| * coolrunner2: Initial fixes for special p-termsRobert Ou2017-09-012-1/+81
| | | | | | | | | | Certain signals can only be controlled by a product term and not a sum-of-products. Do the initial work for fixing this.
| * coolrunner2: Fix mapping of flip-flopsRobert Ou2017-09-011-1/+0
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| * coolrunner2: Combine some for loops togetherRobert Ou2017-09-011-16/+14
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* | Merge pull request #405 from azonenberg/gpak-refactoringClifford Wolf2017-09-025-137/+157
|\ \ | |/ |/| Gpak refactoring
| * Fixed typo in error messageAndrew Zonenberg2017-09-011-1/+1
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