| Commit message (Collapse) | Author | Age | Files | Lines | ||
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| * | | | abc9 to cope with non-wideports, count cells properly | Eddie Hung | 2019-02-16 | 1 | -11/+54 | |
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| * | | | Tidy up write_xaiger | Eddie Hung | 2019-02-16 | 1 | -8/+6 | |
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| * | | | write_aiger() to perform CI/CO post-processing and fix symbols | Eddie Hung | 2019-02-16 | 1 | -7/+17 | |
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| * | | | read_aiger() to cope with constant outputs, mixed wideports, do cleaning | Eddie Hung | 2019-02-16 | 1 | -8/+130 | |
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| * | | | Move lookup inside if | Eddie Hung | 2019-02-15 | 1 | -2/+2 | |
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| * | | | Fixes needed for DFF circuits | Eddie Hung | 2019-02-15 | 1 | -4/+3 | |
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| * | | | Refactor | Eddie Hung | 2019-02-15 | 1 | -29/+32 | |
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| * | | | Cope with width != 1 when re-mapping cells | Eddie Hung | 2019-02-15 | 1 | -11/+25 | |
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| * | | | abc9 to stitch results with CI/CO properly | Eddie Hung | 2019-02-15 | 1 | -16/+32 | |
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| * | | | read_aiger with more asserts, and call clean | Eddie Hung | 2019-02-15 | 1 | -4/+11 | |
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| * | | | write_xaiger to cope with unknown cells by transforming them to CI/CO | Eddie Hung | 2019-02-15 | 1 | -6/+44 | |
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| * | | | More cleanup | Eddie Hung | 2019-02-14 | 1 | -15/+6 | |
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| * | | | More cleanup of write_xaiger | Eddie Hung | 2019-02-14 | 1 | -73/+1 | |
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| * | | | Get rid of formal stuff from xaiger backend | Eddie Hung | 2019-02-14 | 1 | -58/+0 | |
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| * | | | synth_ice40 to have new -abc9 arg | Eddie Hung | 2019-02-14 | 1 | -4/+12 | |
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| * | | | Leave FIXME for clean | Eddie Hung | 2019-02-13 | 1 | -3/+3 | |
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| * | | | Use module->addLut() | Eddie Hung | 2019-02-13 | 1 | -5/+1 | |
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| * | | | Fix stitching | Eddie Hung | 2019-02-13 | 1 | -4/+4 | |
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| * | | | Use ConstEval to compute LUT masks | Eddie Hung | 2019-02-13 | 2 | -63/+69 | |
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| * | | | Merge remote-tracking branch 'origin/read_aiger' into xaig | Eddie Hung | 2019-02-13 | 4 | -17/+12 | |
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| | * | | | Missing headers for Xcode? | Eddie Hung | 2019-02-12 | 1 | -0/+2 | |
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| | * | | | Merge branch 'read_aiger' of github.com:eddiehung/yosys into read_aiger | Eddie Hung | 2019-02-12 | 1 | -3/+1 | |
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| | | * | | | Do not break for constraints | Eddie Hung | 2019-02-11 | 1 | -1/+0 | |
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| | | * | | | No increment line_count for binary ANDs | Eddie Hung | 2019-02-11 | 1 | -1/+1 | |
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| | | * | | | Do not ignore newline after AND in binary AIG | Eddie Hung | 2019-02-11 | 1 | -1/+0 | |
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| | * | | | | Use module->add{Not,And}Gate() functions | Eddie Hung | 2019-02-12 | 1 | -8/+2 | |
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| | * | | | Merge remote-tracking branch 'origin/dff_init' into read_aiger | Eddie Hung | 2019-02-08 | 2 | -7/+7 | |
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| | | * | | Cope WIDTH of ff/latch cells is default of zero | Eddie Hung | 2019-02-06 | 1 | -6/+6 | |
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| | | * | | Remove check for cell->name[0] == '$' | Eddie Hung | 2019-02-06 | 1 | -1/+1 | |
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| * | | | | Merge https://github.com/YosysHQ/yosys into xaig | Eddie Hung | 2019-02-13 | 3 | -44/+47 | |
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| | * | | | Fix sign handling of real constants | Clifford Wolf | 2019-02-13 | 1 | -5/+4 | |
| | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| | * | | | Merge pull request #802 from whitequark/write_verilog_async_mem_ports | Clifford Wolf | 2019-02-12 | 1 | -38/+41 | |
| | |\ \ \ | | | | | | | | | | | write_verilog: correctly emit asynchronous transparent ports | |||||
| | | * | | | write_verilog: correctly emit asynchronous transparent ports. | whitequark | 2019-01-29 | 1 | -38/+41 | |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This commit fixes two related issues: * For asynchronous ports, clock is no longer added to domain list. (This would lead to absurd constructs like `always @(posedge 0)`. * The logic to distinguish synchronous and asynchronous ports is changed to correctly use or avoid clock in all cases. Before this commit, the following RTLIL snippet (after memory_collect) cell $memrd $2 parameter \MEMID "\\mem" parameter \ABITS 2 parameter \WIDTH 4 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 1 parameter \TRANSPARENT 1 connect \CLK 1'0 connect \EN 1'1 connect \ADDR \mem_r_addr connect \DATA \mem_r_data end would lead to invalid Verilog: reg [1:0] _0_; always @(posedge 1'h0) begin _0_ <= mem_r_addr; end assign mem_r_data = mem[_0_]; Note that there are two potential pitfalls remaining after this change: * For asynchronous ports, the \EN input and \TRANSPARENT parameter are silently ignored. (Per discussion in #760 this is the correct behavior.) * For synchronous transparent ports, the \EN input is ignored. This matches the behavior of the $mem simulation cell. Again, see #760. | |||||
| | * | | | | Merge pull request #806 from daveshah1/fsm_opt_no_reset | Clifford Wolf | 2019-02-12 | 1 | -1/+2 | |
| | |\ \ \ \ | | | | | | | | | | | | | fsm_opt: Fix runtime error for FSMs without a reset state | |||||
| | | * | | | | fsm_opt: Fix runtime error for FSMs without a reset state | David Shah | 2019-02-07 | 1 | -1/+2 | |
| | |/ / / / | | | | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me> | |||||
| * | | | | | Rip out some more stuff | Eddie Hung | 2019-02-13 | 1 | -36/+0 | |
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| * | | | | | Rip out unused functions in abc9 | Eddie Hung | 2019-02-12 | 1 | -416/+61 | |
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| * | | | | | Add support for read_aiger -wideports | Eddie Hung | 2019-02-12 | 2 | -6/+15 | |
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| * | | | | | Add support for read_aiger -map | Eddie Hung | 2019-02-12 | 2 | -4/+82 | |
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| * | | | | | Parse 'm' in xaiger | Eddie Hung | 2019-02-12 | 1 | -20/+57 | |
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| * | | | | | WIP for ABC with aiger | Eddie Hung | 2019-02-12 | 1 | -130/+19 | |
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| * | | | | | Add read_xaiger | Eddie Hung | 2019-02-11 | 2 | -27/+108 | |
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| * | | | | | Add write_xaiger | Eddie Hung | 2019-02-11 | 2 | -21/+11 | |
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| * | | | | | Copy backends/aiger/aiger.cc to xaiger.cc | Eddie Hung | 2019-02-08 | 1 | -0/+788 | |
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| * | | | | | Compile abc9 | Eddie Hung | 2019-02-08 | 2 | -8/+9 | |
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| * | | | | | Refactor kernel/cost.h definition into cost.cc | Eddie Hung | 2019-02-08 | 3 | -49/+78 | |
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| * | | | | | Copy abc.cc to abc9.cc | Eddie Hung | 2019-02-08 | 1 | -0/+1868 | |
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| * | | | | addDff -> addDffGate as per @daveshah1 | Eddie Hung | 2019-02-08 | 1 | -1/+1 | |
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| * | | | | Fix tabulation | Eddie Hung | 2019-02-08 | 1 | -28/+28 | |
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| * | | | | -module_name arg to go before -clk_name | Eddie Hung | 2019-02-08 | 1 | -7/+7 | |
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index : iCE40/yosys | |
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