| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | Bugfix in "read_verilog -D NAME=VAL" handling | Clifford Wolf | 2016-11-28 | 1 | -3/+3 |
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| * | Removed shebang line from smtio.py, fixes #279 | Clifford Wolf | 2016-11-27 | 1 | -1/+0 |
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| * | Added wire start_offset and upto handling BLIF back-end | Clifford Wolf | 2016-11-23 | 1 | -1/+1 |
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| * | Added wire start_offset and upto handling to splitnets cmd | Clifford Wolf | 2016-11-23 | 1 | -2/+8 |
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| * | Merge pull request #274 from oldtopman/lcurses | Clifford Wolf | 2016-11-22 | 1 | -0/+5 |
| |\ | | | | | Added optional flag for linking curses with readline. | ||||
| | * | Added optional flag for linking curses with readline. | oldtopman | 2016-11-21 | 1 | -0/+5 |
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| * | | Added "yosys-smtbmc --append" | Clifford Wolf | 2016-11-22 | 1 | -2/+20 |
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| * | Merge pull request #272 from AlexDaniel/master | Clifford Wolf | 2016-11-19 | 1 | -63/+64 |
| |\ | | | | | Markdownify README (№2) | ||||
| | * | Keep lines under 80 characters | Aleks-Daniel Jakimenko-Aleksejev | 2016-11-19 | 1 | -10/+11 |
| | | | | | | | | | | | Recent README changes added some characters to existing lines, which made them longer than 80 characters. This commit fixes that. | ||||
| | * | Markdownify README even further | Aleks-Daniel Jakimenko-Aleksejev | 2016-11-19 | 1 | -60/+60 |
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| * | | Improved ABC default scripts | Clifford Wolf | 2016-11-19 | 1 | -17/+34 |
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| * | | Merge pull request #271 from azidar/bugfix-assign-wmask | Clifford Wolf | 2016-11-19 | 1 | -0/+1 |
| |\ \ | |/ |/| | Bugfix: include assign to write-mask | ||||
| | * | Bugfix: include assign to write-mask | Adam Izraelevitz | 2016-11-18 | 1 | -0/+1 |
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| * | More progress in FIRRTL back-end | Clifford Wolf | 2016-11-18 | 3 | -4/+121 |
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| * | Progress in FIRRTL back-end | Clifford Wolf | 2016-11-18 | 4 | -5/+55 |
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| * | Added first draft of FIRRTL back-end | Clifford Wolf | 2016-11-17 | 2 | -0/+353 |
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| * | Cleanups and fixed in write_verilog regarding reg init | Clifford Wolf | 2016-11-16 | 1 | -15/+61 |
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| * | Added support for hierarchical defparams | Clifford Wolf | 2016-11-15 | 5 | -17/+65 |
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| * | Remember global declarations and defines accross read_verilog calls | Clifford Wolf | 2016-11-15 | 6 | -8/+23 |
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| * | Merge pull request #268 from AlexDaniel/master | Clifford Wolf | 2016-11-13 | 1 | -34/+27 |
| |\ | | | | | Markdownify README | ||||
| | * | Markdownify README | Aleks-Daniel Jakimenko-Aleksejev | 2016-11-12 | 1 | -34/+27 |
| |/ | | | | | This is the first commit in series. There are many other things that could be improved, this is just the first renderable version. | ||||
| * | Minor bugfix in submod | Clifford Wolf | 2016-11-09 | 1 | -0/+1 |
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| * | Progress in examples/gowin/ | Clifford Wolf | 2016-11-08 | 5 | -21/+95 |
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| * | Indenting fixes in gowin sim cell lib | Clifford Wolf | 2016-11-08 | 1 | -20/+28 |
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| * | Bugfix in "setundef" pass | Clifford Wolf | 2016-11-08 | 1 | -2/+7 |
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| * | Added examples/gowin/ | Clifford Wolf | 2016-11-07 | 6 | -0/+57 |
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| * | Implemented "scc -set_attr" | Clifford Wolf | 2016-11-06 | 1 | -22/+32 |
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| * | Bugfix in "scc" command | Clifford Wolf | 2016-11-06 | 1 | -9/+11 |
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| * | Fixed anonymous genblock object names | Clifford Wolf | 2016-11-04 | 1 | -1/+1 |
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| * | Added hex constant support to write_verilog | Clifford Wolf | 2016-11-03 | 2 | -5/+63 |
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| * | We are now in 0.7+ development | Clifford Wolf | 2016-11-03 | 1 | -1/+1 |
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| * | Yosys 0.7 | Clifford Wolf | 2016-11-03 | 1 | -1/+1 |
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| * | Bugfix in "hierarchy -check" | Clifford Wolf | 2016-11-02 | 1 | -1/+1 |
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| * | Updated command reference in manual | Clifford Wolf | 2016-11-02 | 1 | -100/+568 |
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| * | Changelog for Yosys 0.7 | Clifford Wolf | 2016-11-02 | 1 | -0/+99 |
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| * | Added support for fsm_encoding="user" | Clifford Wolf | 2016-11-02 | 1 | -3/+3 |
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| * | Added "fsm_expand -full" | Clifford Wolf | 2016-11-02 | 2 | -17/+35 |
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| * | Some fixes in handling of signed arrays | Clifford Wolf | 2016-11-01 | 2 | -0/+7 |
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| * | iCE40 flow is not experimental anymore | Clifford Wolf | 2016-11-01 | 1 | -1/+1 |
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| * | Added initial version of "synth_gowin" | Clifford Wolf | 2016-11-01 | 4 | -0/+266 |
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| * | Adde "write_verilog -renameprefix -v" | Clifford Wolf | 2016-11-01 | 1 | -5/+23 |
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| * | Added support for (single-clock) transparent memories to bram tests | Clifford Wolf | 2016-11-01 | 2 | -10/+23 |
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| * | Bugfix in fsm_map for FSMs without reset state | Clifford Wolf | 2016-10-25 | 1 | -1/+2 |
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| * | Added avail params to ilang format, check module params in 'hierarchy -check' | Clifford Wolf | 2016-10-22 | 4 | -3/+25 |
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| * | Added "setparam -type" | Clifford Wolf | 2016-10-19 | 1 | -3/+13 |
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| * | No limit for length of lines in BLIF front-end | Clifford Wolf | 2016-10-19 | 1 | -1/+7 |
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| * | Merge pull request #250 from azonenberg/master | Clifford Wolf | 2016-10-19 | 1 | -4/+35 |
| |\ | | | | | Add support for more GreenPak cells (edge detector, delay, pattern generator) | ||||
| | * | Fixed typo in last commit | Andrew Zonenberg | 2016-10-18 | 1 | -1/+1 |
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| | * | greenpak4: Added GP_PGEN cell definition | Andrew Zonenberg | 2016-10-18 | 1 | -0/+21 |
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| | * | Added GLITCH_FILTER parameter to GP_DELAY | Andrew Zonenberg | 2016-10-18 | 1 | -3/+2 |
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index : iCE40/yosys | |
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