iCE40/yosys - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
*	Add -noautowire option to verilog frontend	Marcus Comstedt	2015-08-01	1	-1/+8
*	Added WORDS parameter to $meminit	Clifford Wolf	2015-07-31	6	-16/+95
*	Fixed flatten $meminit handling	Clifford Wolf	2015-07-30	1	-1/+1
*	Improvements in BLIF back-end	Clifford Wolf	2015-07-29	1	-5/+84
*	Fixed nested mem2reg	Clifford Wolf	2015-07-29	2	-4/+11
*	Don't write a 17th memory bit in ice40/cells_sim (by Larry Doolittle)	Clifford Wolf	2015-07-27	1	-1/+0
*	Fixed "check" command for inout ports	Clifford Wolf	2015-07-27	1	-3/+11
*	Some cleanups in opt_rmdff	Clifford Wolf	2015-07-25	1	-16/+9
*	Added "miter -assert"	Clifford Wolf	2015-07-25	1	-1/+93
*	Keep modules with $assume (like $assert)	Clifford Wolf	2015-07-25	1	-1/+1
*	Improved $adff simplification	Clifford Wolf	2015-07-24	1	-1/+1
*	iCE40 DFF sim models: init Q regs to 0	Clifford Wolf	2015-07-20	1	-20/+43
*	Fixed techmap processes error msg	Clifford Wolf	2015-07-18	1	-2/+3
*	Avoid tristate warning for blackbox ice40/cells_sim.v	Clifford Wolf	2015-07-18	1	-0/+2
*	Some fixes in "select" command	Clifford Wolf	2015-07-16	1	-1/+3
*	Fixed YosysJS.create_worker() usage of this.url_prefix	Clifford Wolf	2015-07-10	1	-1/+1
*	Improved liberty file test case	Clifford Wolf	2015-07-06	1	-1/+2
*	Updated ABC	Clifford Wolf	2015-07-06	1	-1/+1
*	Do not collect disabled $memwr cells	Clifford Wolf	2015-07-06	1	-15/+18
*	Improved YosysJS WebWorker API	Clifford Wolf	2015-07-04	3	-10/+51
*	Bugfix in fsm_extract	Clifford Wolf	2015-07-03	1	-3/+16
*	Added "synth -nofsm"	Clifford Wolf	2015-07-02	1	-1/+10
*	Fixed trailing whitespaces	Clifford Wolf	2015-07-02	195	-729/+729
*	Added opt_const -clkinv	Clifford Wolf	2015-07-01	2	-6/+95
*	Added logic-loop error handling to freduce	Clifford Wolf	2015-06-30	1	-0/+11
*	Merge branch 'master' of github.com:cliffordwolf/yosys	Clifford Wolf	2015-06-30	3	-33/+145
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\| *	Added YosysJS.create_worker()	Clifford Wolf	2015-06-28	3	-33/+145
* \|	Bugfix in chparam	Clifford Wolf	2015-06-30	1	-6/+5
* \|	Added design->rename(module, new_name)	Clifford Wolf	2015-06-30	3	-3/+9
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*	iCE40: set min bram efficiency to 2%	Clifford Wolf	2015-06-20	1	-2/+2
*	Using static mem size of 128 MB in emcc build	Clifford Wolf	2015-06-20	1	-1/+1
*	Added init support to SMV back-end	Clifford Wolf	2015-06-19	1	-1/+3
*	Progress in SMV back-end	Clifford Wolf	2015-06-19	1	-64/+115
*	Progress in SMV back-end	Clifford Wolf	2015-06-19	2	-14/+60
*	Progress in SMV back-end	Clifford Wolf	2015-06-18	4	-24/+147
*	Progress in SMV back-end	Clifford Wolf	2015-06-17	1	-11/+72
*	Added "rename -top new_name"	Clifford Wolf	2015-06-17	3	-0/+43
*	Progress in SMV back-end	Clifford Wolf	2015-06-17	1	-11/+64
*	Progress in SMV back-end	Clifford Wolf	2015-06-16	1	-3/+46
*	Added "synth -nordff -noalumacc"	Clifford Wolf	2015-06-15	1	-3/+20
*	Progress in SMV back-end	Clifford Wolf	2015-06-15	1	-2/+95
*	Progress in SMV back-end	Clifford Wolf	2015-06-15	1	-7/+85
*	Added "write_smv" skeleton	Clifford Wolf	2015-06-15	3	-2/+265
*	Removed debug code from write_smt2	Clifford Wolf	2015-06-14	1	-2/+0
*	Modernized memory_dff (and fixed a bug)	Clifford Wolf	2015-06-14	2	-151/+166
*	Added "memory -nordff"	Clifford Wolf	2015-06-14	1	-2/+9
*	Added write_smt2 -mem	Clifford Wolf	2015-06-14	1	-80/+157
*	Makefile fix for YosysJS build	Clifford Wolf	2015-06-11	1	-0/+4
*	Fixed cstr_buf for std::string with small string optimization	Clifford Wolf	2015-06-11	6	-5/+16
*	Improvements in cellaigs.cc and "json -aig"	Clifford Wolf	2015-06-11	2	-10/+215