| Commit message (Collapse) | Author | Age | Files | Lines | ||
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| | | * | | update test | Pepijn de Vos | 2019-12-03 | 1 | -2/+3 | |
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| | | * | | Use -match-init to not synth contradicting init values | Pepijn de Vos | 2019-12-03 | 2 | -11/+13 | |
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| | | * | | attempt to fix formatting | Pepijn de Vos | 2019-11-25 | 2 | -292/+292 | |
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| | | * | | gowin: add and test dff init values | Pepijn de Vos | 2019-11-25 | 4 | -41/+495 | |
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| | * | | | Merge pull request #1542 from YosysHQ/dave/abc9-loop-fix | David Shah | 2019-12-02 | 2 | -29/+46 | |
| | |\ \ \ | | | | | | | | | | | abc9: Fix breaking of SCCs | |||||
| | | * | | | abc9: Fix breaking of SCCs | David Shah | 2019-12-01 | 2 | -29/+46 | |
| | | | |/ | | |/| | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me> | |||||
| | * | | | Merge pull request #1539 from YosysHQ/mwk/ilang-bounds-check | Clifford Wolf | 2019-12-01 | 1 | -0/+4 | |
| | |\ \ \ | | |/ / | |/| | | read_ilang: do bounds checking on bit indices | |||||
| | | * | | read_ilang: do bounds checking on bit indices | Marcin Kościelnicki | 2019-11-27 | 1 | -0/+4 | |
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| | * | | | Merge pull request #1540 from YosysHQ/mwk/xilinx-bufpll | Miodrag Milanović | 2019-11-29 | 2 | -0/+21 | |
| | |\ \ \ | | | | | | | | | | | xilinx: Add missing blackbox cell for BUFPLL. | |||||
| | | * | | | xilinx: Add missing blackbox cell for BUFPLL. | Marcin Kościelnicki | 2019-11-29 | 2 | -0/+21 | |
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| | * | | | | Revert "Fold loop" | Eddie Hung | 2019-11-27 | 1 | -3/+6 | |
| | | |/ / | |/| | | | | | | | | | | This reverts commit a30d5e1cc35791a98b2269c5e587c566fe8b0a35. | |||||
| * | | | | Call abc9 with "&write -n", and parse_xaiger() to cope | Eddie Hung | 2019-12-06 | 2 | -94/+87 | |
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| * | | | | Remove creation of $abc9_control_wire | Eddie Hung | 2019-12-06 | 1 | -16/+6 | |
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| * | | | | Do not connect undriven POs to 1'bx | Eddie Hung | 2019-12-06 | 1 | -8/+3 | |
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| * | | | | Fix abc9 re-integration, remove abc9_control_wire, use cell->type as | Eddie Hung | 2019-12-06 | 1 | -39/+15 | |
| | | | | | | | | | | | | | | | | | as part of clock domain for mergeability class | |||||
| * | | | | Fix writing non-whole modules, including inouts and keeps | Eddie Hung | 2019-12-06 | 1 | -90/+81 | |
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| * | | | | abc9 to use mergeability class to differentiate sync/async | Eddie Hung | 2019-12-06 | 1 | -12/+15 | |
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| * | | | | write_xaiger to support part-selected modules again | Eddie Hung | 2019-12-05 | 1 | -11/+37 | |
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| * | | | | abc9 to do clock partitioning again | Eddie Hung | 2019-12-05 | 1 | -37/+144 | |
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| * | | | | Remove clkpart | Eddie Hung | 2019-12-05 | 3 | -313/+0 | |
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| * | | | | Revert "Special abc9_clock wire to contain only clock signal" | Eddie Hung | 2019-12-05 | 1 | -10/+12 | |
| | | | | | | | | | | | | | | | | | This reverts commit 6a2eb5d8f9286b9574647c03e2bdc8b63fccbe4d. | |||||
| * | | | | Missing wire declaration | Eddie Hung | 2019-12-04 | 1 | -0/+1 | |
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| * | | | | abc9_map.v to transform INIT=1 to INIT=0 | Eddie Hung | 2019-12-04 | 2 | -118/+292 | |
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| * | | | | Oh deary me | Eddie Hung | 2019-12-04 | 1 | -4/+4 | |
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| * | | | | Bump ABC to get "&verify -s" fix | Eddie Hung | 2019-12-04 | 1 | -1/+1 | |
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| * | | | | output reg Q -> output Q to suppress warning | Eddie Hung | 2019-12-04 | 1 | -8/+8 | |
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| * | | | | abc9_map.v to do `zinit' and make INIT = 1'b0 | Eddie Hung | 2019-12-04 | 1 | -70/+112 | |
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| * | | | | Cleanup | Eddie Hung | 2019-12-03 | 1 | -11/+12 | |
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| * | | | | Add assertion | Eddie Hung | 2019-12-03 | 1 | -0/+1 | |
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| * | | | | write_xaiger to consume abc9_init attribute for abc9_flops | Eddie Hung | 2019-12-03 | 1 | -34/+28 | |
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| * | | | | Add abc9_init wire, attach to abc9_flop cell | Eddie Hung | 2019-12-03 | 2 | -4/+24 | |
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| * | | | | Revert "Add INIT value to abc9_control" | Eddie Hung | 2019-12-03 | 1 | -8/+8 | |
| | | | | | | | | | | | | | | | | | This reverts commit 19bfb4195818be12e6fb962de29ca32444498c22. | |||||
| * | | | | Update ABCREV for upstream bugfix | Eddie Hung | 2019-12-03 | 1 | -1/+1 | |
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| * | | | | techmap abc_unmap.v before xilinx_srl -fixed | Eddie Hung | 2019-12-03 | 1 | -6/+5 | |
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| * | | | | Add INIT value to abc9_control | Eddie Hung | 2019-12-02 | 1 | -8/+8 | |
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| * | | | | Cleanup | Eddie Hung | 2019-12-01 | 1 | -3/+2 | |
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| * | | | | Use pool instead of std::set for determinism | Eddie Hung | 2019-12-01 | 1 | -1/+1 | |
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| * | | | | Use pool<> not std::set<> for determinism | Eddie Hung | 2019-12-01 | 1 | -4/+4 | |
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| * | | | | clkpart -unpart into 'finalize' | Eddie Hung | 2019-11-28 | 1 | -3/+4 | |
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| * | | | | Merge remote-tracking branch 'origin/eddie/submod_po' into xaig_dff | Eddie Hung | 2019-11-28 | 1 | -1/+1 | |
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| | * | | | | Move \init signal for non-port signals as long as internally driven | Eddie Hung | 2019-11-28 | 1 | -1/+1 | |
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| * | | | | | Merge remote-tracking branch 'origin/eddie/submod_po' into xaig_dff | Eddie Hung | 2019-11-27 | 1 | -0/+31 | |
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| | * | | | | Fix multiple driver issue | Eddie Hung | 2019-11-27 | 1 | -2/+7 | |
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| | * | | | | Add multiple driver testcase | Eddie Hung | 2019-11-27 | 1 | -0/+31 | |
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| * | | | | | Fix multiple driver issue | Eddie Hung | 2019-11-27 | 1 | -2/+7 | |
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| * | | | | | Add comment, use sigmap | Eddie Hung | 2019-11-27 | 1 | -2/+2 | |
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| * | | | | | Revert "Fold loop" | Eddie Hung | 2019-11-27 | 1 | -3/+6 | |
| | | | | | | | | | | | | | | | | | | | | | This reverts commit da51492dbcc9f19a4808ef18e8ae1222bc55b118. | |||||
| * | | | | | Merge remote-tracking branch 'origin/master' into xaig_dff | Eddie Hung | 2019-11-27 | 5 | -7/+100 | |
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| | * | | | | Merge pull request #1536 from YosysHQ/eddie/xilinx_dsp_muladd | Eddie Hung | 2019-11-27 | 2 | -3/+72 | |
| | |\ \ \ \ | | | | | | | | | | | | | xilinx_dsp: consider sign and zero-extension when packing post-multiplier adder | |||||
| | | * | | | | No need for -abc9 | Eddie Hung | 2019-11-26 | 1 | -1/+1 | |
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index : iCE40/yosys | |
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