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* Remove &verify -sEddie Hung2019-12-171-1/+1
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* Bump ABC for upstream fixEddie Hung2019-12-171-1/+1
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* Use pool<> instead of std::set<> to preserver orderingEddie Hung2019-12-171-6/+6
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* aiger frontend to user shorter, $-prefixed, namesEddie Hung2019-12-171-14/+14
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* Cleanup xaiger, remove unnecessary complexity with inoutEddie Hung2019-12-172-84/+24
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* read_xaiger to cope with optional '\n' after 'c'Eddie Hung2019-12-171-2/+2
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* Do not sigmapEddie Hung2019-12-171-1/+1
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* Revert "Use sigmap signal"Eddie Hung2019-12-171-1/+1
| | | | This reverts commit 42f990f3a6b7928841fa0e290fa2688925485907.
* abc9 needs a clean afterwardsEddie Hung2019-12-161-2/+4
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* Put $__ABC9_{FF_,ASYNC} into same clock domain as abc9_flopEddie Hung2019-12-161-5/+27
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* Use sigmap signalEddie Hung2019-12-161-1/+1
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* Skip $inout transformation if not a PIEddie Hung2019-12-161-3/+5
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* Revert "write_xaiger: use sigmap bits more consistently"Eddie Hung2019-12-161-4/+5
| | | | This reverts commit 6c340112fee1bb8989cbd41923aaa627d77d5110.
* write_xaiger: use sigmap bits more consistentlyEddie Hung2019-12-161-5/+4
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* Name inputs/outputs of aiger 'i%d' and 'o%d'Eddie Hung2019-12-131-13/+6
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* Remove 'clkpart' entry in CHANGELOGEddie Hung2019-12-121-1/+0
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* Merge remote-tracking branch 'origin/master' into xaig_dffEddie Hung2019-12-1218-64/+238
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| * abc9_map.v: fix Xilinx LUTRAMEddie Hung2019-12-121-6/+6
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| * Update README.md :: abc_ -> abc9_Eddie Hung2019-12-111-3/+3
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| * Fix bitwidth mismatch; suppresses iverilog warningEddie Hung2019-12-111-4/+4
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| * Merge pull request #1564 from ZirconiumX/intel_housekeepingDavid Shah2019-12-118-6/+6
| |\ | | | | | | Intel housekeeping
| | * synth_intel: a10gx -> arria10gxDan Ravensloft2019-12-105-4/+4
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| | * synth_intel: cyclone10 -> cyclone10lpDan Ravensloft2019-12-105-4/+4
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| * | Merge pull request #1545 from YosysHQ/eddie/ice40_wrapcarry_attrEddie Hung2019-12-098-51/+225
| |\ \ | | | | | | | | Preserve SB_CARRY name and attributes when using $__ICE40_CARRY_WRAPPER
| | * | ice40_opt to restore attributes/name when unwrappingEddie Hung2019-12-091-0/+15
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| | * | ice40_wrapcarry -unwrap to preserve 'src' attributeEddie Hung2019-12-091-1/+9
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| | * | unmap $__ICE40_CARRY_WRAPPER in testEddie Hung2019-12-091-1/+21
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| | * | -unwrap to create $lut not SB_LUT4 for opt_lutEddie Hung2019-12-091-7/+5
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| | * | Sensitive to direct inst of $__ICE40_CARRY_WRAPPER; recreate SB_LUT4Eddie Hung2019-12-092-8/+12
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| | * | ice40_wrapcarry to really preserve attributes via -unwrap optionEddie Hung2019-12-094-39/+61
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| | * | Drop keep=0 attributes on SB_CARRYEddie Hung2019-12-062-2/+10
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| | * | Merge SB_CARRY+SB_LUT4's attributes when creating $__ICE40_CARRY_WRAPPEREddie Hung2019-12-051-0/+1
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| | * | Add WIP test for unwrapping $__ICE40_CARRY_WRAPPEREddie Hung2019-12-051-0/+30
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| | * | Check SB_CARRY name also preservedEddie Hung2019-12-031-0/+1
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| | * | $__ICE40_CARRY_WRAPPER to use _TECHMAP_REPLACE_ for SB_CARRY to preserveEddie Hung2019-12-031-1/+1
| | | | | | | | | | | | | | | | name and attr
| | * | ice40_opt to ignore (* keep *) -ed cellsEddie Hung2019-12-031-0/+5
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| | * | ice40_wrapcarry to preserve SB_CARRY's attributesEddie Hung2019-12-031-0/+2
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| | * | Add testcaseEddie Hung2019-12-031-0/+60
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* | | | abc9_map.v: fix Xilinx LUTRAMEddie Hung2019-12-121-6/+6
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* | | | Fix commentEddie Hung2019-12-091-1/+1
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* | | | Merge remote-tracking branch 'origin/master' into xaig_dffEddie Hung2019-12-0619-971/+1773
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| * | | Merge pull request #1555 from antmicro/fix-macc-xilinx-testEddie Hung2019-12-061-1/+1
| |\ \ \ | | | | | | | | | | tests: arch: xilinx: Change order of arguments in macc.sh
| | * | | tests: arch: xilinx: Change order of arguments in macc.shJan Kowalewski2019-12-061-1/+1
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| * | | Merge pull request #1551 from whitequark/manual-cell-operandsClifford Wolf2019-12-053-43/+82
| |\ \ \ | | |_|/ | |/| | Clarify semantics of comb cells, in particular shifts
| | * | kernel: require \B_SIGNED=0 on $shl, $sshl, $shr, $sshr.whitequark2019-12-042-8/+26
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Before this commit, these cells would accept any \B_SIGNED and in case of \B_SIGNED=1, would still treat the \B input as unsigned. Also fix the Verilog frontend to never emit such constructs.
| | * | manual: document behavior of many comb cells more precisely.whitequark2019-12-041-35/+56
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| * | | xilinx: Add tristate buffer mapping. (#1528)Marcin Kościelnicki2019-12-042-9/+16
| | | | | | | | | | | | Fixes #1225.
| * | | iopadmap: Refactor and fix tristate buffer mapping. (#1527)Marcin Kościelnicki2019-12-042-146/+196
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The previous code for rerouting wires when inserting tristate buffers was overcomplicated and didn't handle all cases correctly (in particular, only cell connections were rewired — internal connections were not).
| * | | xilinx: Add models for LUTRAM cells. (#1537)Marcin Kościelnicki2019-12-043-624/+831
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| * | Merge pull request #1524 from pepijndevos/gowindffinitClifford Wolf2019-12-035-114/+571
| |\ \ | | | | | | | | Gowin: add and test DFF init values
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