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* Merge pull request #1184 from whitequark/synth-better-labelsClifford Wolf2019-07-185-17/+21
|\ | | | | synth_{ice40,ecp5}: more sensible pass label naming
| * synth_ecp5: rename dram to lutram everywhere.whitequark2019-07-164-13/+13
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| * synth_{ice40,ecp5}: more sensible pass label naming.whitequark2019-07-162-5/+9
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* | Merge pull request #1203 from whitequark/write_verilog-zero-width-valuesClifford Wolf2019-07-181-1/+2
|\ \ | | | | | | write_verilog: dump zero width constants correctly
| * | write_verilog: dump zero width constants correctly.whitequark2019-07-161-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Before this commit, zero width constants were dumped as "" (empty string). Unfortunately, 1364-2005 5.2.3.3 indicates that an empty string is equivalent to "\0", and is 8 bits wide, so that's wrong. After this commit, a replication operation with a count of zero is used instead, which is explicitly permitted per 1364-2005 5.1.14, and is defined to have size zero. (Its operand has to have a non-zero size for it to be legal, though.) Fixes #948 (again).
* | | Remove old $pmux_safe code from write_verilogClifford Wolf2019-07-171-5/+4
| | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | | Merge pull request #1204 from smunaut/fix_1187David Shah2019-07-172-4/+4
|\ \ \ | |/ / |/| | ice40: Adapt the relut process passes to the new $lut/SB_LUT4 port map
| * | ice40: Adapt the relut process passes to the new $lut <=> SB_LUT4 port mapSylvain Munaut2019-07-162-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The new mapping introduced in 437fec0d88b4a2ad172edf0d1a861a38845f3b1d needed matching adaptation when converting and optimizing LUTs during the relut process Fixes #1187 (Diagnosis of the issue by @daveshah1 on IRC) Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
* | | Merge pull request #1202 from YosysHQ/cmp2lut_lut6Eddie Hung2019-07-164-24/+37
|\ \ \ | |/ / |/| | cmp2lut transformation to support >32 bit LUT masks
| * | gen_lut to return correctly sized LUT maskEddie Hung2019-07-161-1/+1
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| * | Forgot to commitEddie Hung2019-07-161-0/+7
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| * | Add tests for cmp2lut on LUT6Eddie Hung2019-07-162-23/+29
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* | Merge pull request #1188 from YosysHQ/eddie/abc9_push_invertersEddie Hung2019-07-162-45/+128
|\ \ | | | | | | abc9: push inverters driving box inputs (comb outputs) through $lut soft logic
| * | Add commentEddie Hung2019-07-131-0/+5
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| * | Update test with more accurate LUT maskEddie Hung2019-07-121-1/+1
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| * | duplicate -> cloneEddie Hung2019-07-121-3/+3
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| * | More cleanupEddie Hung2019-07-121-8/+2
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| * | CleanupEddie Hung2019-07-121-29/+51
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| * | CleanupEddie Hung2019-07-121-10/+4
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| * | CleanupEddie Hung2019-07-121-15/+24
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| * | More cleanupEddie Hung2019-07-121-11/+10
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| * | CleanupEddie Hung2019-07-121-46/+16
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| * | CleanupEddie Hung2019-07-121-7/+1
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| * | CleanupEddie Hung2019-07-121-13/+109
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* | Merge pull request #1186 from YosysHQ/eddie/abc9_ice40_fixEddie Hung2019-07-169-31/+122
|\ \ | | | | | | abc9/ice40: encapsulate SB_CARRY+SB_LUT4 into one box
| * | $__ICE40_CARRY_LUT4 -> $__ICE40_FULL_ADDER as per @whitequarkEddie Hung2019-07-157-8/+8
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| * | ice40_opt to $__ICE40_CARRY_LUT4 into $lut not SB_LUTEddie Hung2019-07-131-9/+7
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| * | Do not double count cells in abcEddie Hung2019-07-121-2/+2
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| * | Use Const::from_string() not its constructor...Eddie Hung2019-07-121-1/+1
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| * | Off by oneEddie Hung2019-07-121-1/+1
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| * | Fix spacingEddie Hung2019-07-121-1/+1
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| * | Remove double pushEddie Hung2019-07-121-1/+0
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| * | Map to and from this box if -abc9Eddie Hung2019-07-121-2/+3
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| * | ice40_opt to handle this box and opt back to SB_LUT4Eddie Hung2019-07-121-0/+48
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| * | Add new box to cells_sim.vEddie Hung2019-07-121-2/+25
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| * | _ABC macro will map and unmap to this new boxEddie Hung2019-07-122-0/+34
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| * | Combine SB_CARRY+SB_LUT into one $__ICE40_CARRY_LUT4 boxEddie Hung2019-07-123-25/+13
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* | | Merge pull request #1200 from mmicko/fix_typo_liberty_ccClifford Wolf2019-07-161-1/+1
|\ \ \ | | | | | | | | Fix typo, double "of"
| * | | Fix typo, double "of"Miodrag Milanovic2019-07-161-1/+1
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* | | | Merge pull request #1199 from mmicko/extract_fa_fixClifford Wolf2019-07-161-2/+2
|\ \ \ \ | |/ / / |/| | | Fix check logic in extract_fa
| * | | Fix check logic in extract_faMiodrag Milanovic2019-07-161-2/+2
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* | | Merge pull request #1196 from YosysHQ/eddie/fix1178Eddie Hung2019-07-151-5/+12
|\ \ \ | | | | | | | | Fix different synth results between with and without debug output "-g"
| * | | Revert "Add log_checkpoint function and use it in opt_muxtree"Eddie Hung2019-07-153-9/+0
| | | | | | | | | | | | | | | | This reverts commit 0e6c83027f24cdf7082606a5631468ad28f41574.
| * | | Revert "Fix first divergence in #1178"Eddie Hung2019-07-151-5/+1
| | | | | | | | | | | | | | | | This reverts commit 1122a2e0671ed00b7c03658f5012e34df12f26de.
| * | | Merge branch 'master' into eddie/fix1178Eddie Hung2019-07-1526-93/+1204
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| * | | | Redesign log_id_cache so that it doesn't keep IdString instances referenced, ↵Clifford Wolf2019-07-151-6/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | fixes #1178 Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | | | Add log_checkpoint function and use it in opt_muxtreeClifford Wolf2019-07-153-0/+9
| | | | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | | | Fix first divergence in #1178Eddie Hung2019-07-091-1/+5
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* | | | | Merge pull request #1189 from YosysHQ/eddie/fix1151Clifford Wolf2019-07-151-0/+4
|\ \ \ \ \ | | | | | | | | | | | | Error out if enable > dbits in memory_bram file
| * | | | | Error out if enable > dbitsEddie Hung2019-07-131-0/+4
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