| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | Improve simplec back-end | Clifford Wolf | 2017-05-12 | 3 | -12/+78 |
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| * | Added support for more gate types to simplec back-end | Clifford Wolf | 2017-05-12 | 1 | -1/+88 |
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| * | Add first draft of simple C back-end | Clifford Wolf | 2017-05-12 | 6 | -0/+623 |
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| * | Update ABC to hg rev e79576e10d72 | Clifford Wolf | 2017-05-11 | 1 | -1/+1 |
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| * | Fix boolector support in yosys-smtbmc | Clifford Wolf | 2017-05-08 | 1 | -18/+18 |
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| * | Add support for localparam in module header | Clifford Wolf | 2017-04-30 | 1 | -1/+7 |
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| * | Fix equiv_simple, old behavior now available with "equiv_simple -short" | Clifford Wolf | 2017-04-28 | 1 | -10/+41 |
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| * | Add support for `resetall compiler directive | Clifford Wolf | 2017-04-26 | 1 | -0/+7 |
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| * | Replace CRLF line endings with LF in de2i.qsf (quartus example) | Clifford Wolf | 2017-04-12 | 1 | -1098/+1098 |
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| * | Squelch trailing whitespace | Larry Doolittle | 2017-04-12 | 19 | -165/+165 |
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| * | Add MAX10 and Cyclone IV items to CHANGELOG | Clifford Wolf | 2017-04-07 | 1 | -0/+13 |
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| * | Merge pull request #337 from dh73/master | Clifford Wolf | 2017-04-07 | 25 | -0/+2255 |
| |\ | | | | | Add initial support for both MAX10 and Cyclone IV (E|GX) FPGAs | ||||
| | * | Add initial support for both MAX10 and Cyclone IV (E|GX) FPGAs | dh73 | 2017-04-05 | 25 | -0/+2255 |
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| * | Add ConstEval defaultval feature | Clifford Wolf | 2017-04-05 | 1 | -1/+8 |
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| * | Fix gcc compiler warning | Clifford Wolf | 2017-04-05 | 1 | -1/+1 |
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| * | Add front-end detection for *.tcl files | Clifford Wolf | 2017-03-28 | 1 | -1/+6 |
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| * | Add minisat 00_PATCH_typofixes.patch | Clifford Wolf | 2017-03-27 | 2 | -0/+21 |
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| * | Remove use of <fpu_control.h> in minisat | Clifford Wolf | 2017-03-27 | 4 | -18/+44 |
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| * | Add "write_smt2 -stdt" mode | Clifford Wolf | 2017-03-20 | 2 | -37/+84 |
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| * | Add generation of logic cells to EDIF back-end runtest.py | Clifford Wolf | 2017-03-19 | 1 | -2/+6 |
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| * | Fix EDIF: portRef member 0 is always the MSB bit | Clifford Wolf | 2017-03-19 | 2 | -13/+14 |
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| * | Add simple EDIF test case generator and checker | Clifford Wolf | 2017-03-18 | 1 | -0/+113 |
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| * | Fix verilog pre-processor for multi-level relative includes | Clifford Wolf | 2017-03-14 | 1 | -4/+26 |
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| * | Improve smt2 encodings of assert/assume/cover, better wire_smt2 help msg | Clifford Wolf | 2017-03-04 | 2 | -33/+87 |
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| * | Add write_aiger $anyseq support | Clifford Wolf | 2017-03-02 | 1 | -0/+7 |
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| * | Allow $anyconst, etc. in non-formal SV mode | Clifford Wolf | 2017-03-01 | 1 | -1/+1 |
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| * | Disable opt_merge for $anyseq and $anyconst | Clifford Wolf | 2017-02-28 | 1 | -0/+3 |
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| * | Use hex addresses in smtbmc vcd mem traces | Clifford Wolf | 2017-02-28 | 1 | -1/+1 |
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| * | Add "chformal -assert2assume" and friends | Clifford Wolf | 2017-02-28 | 1 | -0/+44 |
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| * | Add "chformal" pass | Clifford Wolf | 2017-02-27 | 2 | -0/+239 |
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| * | Add smtbmc support for memory vcd dumping | Clifford Wolf | 2017-02-26 | 1 | -0/+98 |
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| * | Fix extra newline bug in write_smt2 | Clifford Wolf | 2017-02-26 | 1 | -1/+1 |
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| * | Fix bug in smtio unroll code | Clifford Wolf | 2017-02-26 | 1 | -3/+2 |
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| * | Fix assert checking in "yosys-smtbmc -c --append" | Clifford Wolf | 2017-02-26 | 1 | -1/+1 |
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| * | Improve (and fix for stbv mode) SMT2 memory API | Clifford Wolf | 2017-02-26 | 3 | -47/+51 |
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| * | Add support for "yosys-smtbmc -c --append" | Clifford Wolf | 2017-02-25 | 1 | -1/+13 |
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| * | Update ABC to hg rev 3a95bfa55df7 | Clifford Wolf | 2017-02-25 | 1 | -1/+1 |
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| * | Merge branch 'klammerj-master' | Clifford Wolf | 2017-02-25 | 1 | -56/+106 |
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| | * | Improve "write_edif" help message | Clifford Wolf | 2017-02-25 | 1 | -7/+2 |
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| | * | Move EdifNames out of double-private namespace | Clifford Wolf | 2017-02-25 | 1 | -48/+45 |
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| | * | Clean up edif code, swap bit indexing of "upto" ports | Clifford Wolf | 2017-02-25 | 1 | -17/+35 |
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| | * | Merge branch 'master' of https://github.com/klammerj/yosys into klammerj-master | Clifford Wolf | 2017-02-25 | 1 | -6/+46 |
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| | * | Did as you requested, /but/... | Johann Klammer | 2017-02-24 | 2 | -48/+32 |
| | | | | | | | | | Now the nets are wired in reverse again because the netlister still uses zero-based indices. | ||||
| | * | add options for edif flavors | Johann Klammer | 2017-02-23 | 2 | -7/+63 |
| | | | | | | | | | | | | | *to force renames on wide ports *to choose array delimiters *to choose up or downwards indices | ||||
| * | | Merge branch 'master' of github.com:cliffordwolf/yosys | Clifford Wolf | 2017-02-25 | 1 | -3/+4 |
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| | * \ | Merge pull request #322 from azonenberg/master | Clifford Wolf | 2017-02-24 | 1 | -3/+4 |
| | |\ \ | | | | | | | | | Add POUT to GP_COUNTx cells | ||||
| | | * \ | Merge https://github.com/cliffordwolf/yosys | Andrew Zonenberg | 2017-02-24 | 7 | -37/+113 |
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| | | * \ \ | Merge https://github.com/cliffordwolf/yosys | Andrew Zonenberg | 2017-02-16 | 2 | -3/+9 |
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| | | * \ \ \ | Merge https://github.com/cliffordwolf/yosys | Andrew Zonenberg | 2017-02-14 | 11 | -47/+240 |
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| | | * \ \ \ \ | Merge https://github.com/cliffordwolf/yosys | Andrew Zonenberg | 2017-02-11 | 10 | -58/+273 |
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index : iCE40/yosys | |
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