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* Refactor into AigerReader classEddie Hung2019-02-082-79/+92
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* Parse binary AIG filesEddie Hung2019-02-081-49/+164
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* Add binary AIGs converted from AAGEddie Hung2019-02-0814-0/+51
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* Refactor to parse_aiger_header()Eddie Hung2019-02-081-26/+32
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* Add commentEddie Hung2019-02-081-0/+1
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* Handle reset logic in latchesEddie Hung2019-02-081-2/+17
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* Change literal vars from int to unsignedEddie Hung2019-02-081-1/+1
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* Create clk outside of latch loopEddie Hung2019-02-081-7/+9
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* Handle latch symbols tooEddie Hung2019-02-081-3/+1
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* Remove return after log_errorEddie Hung2019-02-081-27/+9
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* Add support for symbol tablesEddie Hung2019-02-081-1/+49
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* Stub for binary AIGEREddie Hung2019-02-081-3/+8
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* RefactorEddie Hung2019-02-061-1/+8
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* Merge branch 'dff_init' of https://github.com/eddiehung/yosys into xaigEddie Hung2019-02-067-50/+172
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| * RefactorEddie Hung2019-02-061-21/+5
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| * write_verilog to cope with init attr on q when -noexprEddie Hung2019-02-061-2/+32
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| * Add INIT parameter to all ff/latch cellsEddie Hung2019-02-062-43/+86
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| * Add tests for simple cases using defparamEddie Hung2019-02-061-0/+21
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| * Add -B option to autotest.sh to append to backend_optsEddie Hung2019-02-061-2/+4
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| * Extend testcaseEddie Hung2019-02-061-2/+34
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| * Add testcaseEddie Hung2019-02-061-0/+10
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| * Add missing blackslash-to-slash convertion to smtio.py (matching ↵Clifford Wolf2019-02-061-1/+1
| | | | | | | | | | | | Smt2Worker::get_id() behavior) Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | Revert most of autotest.sh; for non *.v use Yosys to translateEddie Hung2019-02-061-7/+9
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* | Rename ASCII testsEddie Hung2019-02-0615-0/+0
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* | WIPEddie Hung2019-02-063-0/+247
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* | Add testsEddie Hung2019-02-0416-8/+109
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* Merge pull request #798 from mmicko/masterClifford Wolf2019-01-271-1/+1
|\ | | | | Fixed Anlogic simulation model
| * Fixed Anlogic simulation modelMiodrag Milanovic2019-01-251-1/+1
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* | Merge pull request #800 from whitequark/write_verilog_tribufClifford Wolf2019-01-271-0/+12
|\ \ | | | | | | write_verilog: write $tribuf cell as ternary
| * | write_verilog: write $tribuf cell as ternary.whitequark2019-01-271-0/+12
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* | | Merge branch 'whitequark-write_verilog_keyword'Clifford Wolf2019-01-275-69/+27
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| * | Remove asicworld tests for (unsupported) switch-level modellingClifford Wolf2019-01-274-69/+0
| | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | write_verilog: escape names that match SystemVerilog keywords.whitequark2019-01-271-0/+27
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* | Merge pull request #796 from whitequark/proc_clean_typoDavid Shah2019-01-251-1/+1
|\ \ | |/ |/| proc_clean: fix critical typo
| * proc_clean: fix critical typo.whitequark2019-01-231-1/+1
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* Merge pull request #793 from whitequark/proc_clean_fix_fully_defClifford Wolf2019-01-191-1/+7
|\ | | | | proc_clean: fix fully def check to consider compare/signal length
| * proc_clean: fix fully def check to consider compare/signal length.whitequark2019-01-181-1/+7
|/ | | | Fixes #790.
* Cleanups in igloo2 example designClifford Wolf2019-01-176-7/+4
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Add SF2 IO buffer insertionClifford Wolf2019-01-176-3/+171
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Improve Igloo2 exampleClifford Wolf2019-01-178-22/+41
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Add "synth_sf2 -vlog", fix "synth_sf2 -edif"Clifford Wolf2019-01-171-2/+17
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Add "write_edif -gndvccy"Clifford Wolf2019-01-171-5/+13
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Add optional nullstr argument to log_id()Clifford Wolf2019-01-151-1/+3
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Fix handling of $shiftx in Verilog back-endClifford Wolf2019-01-151-3/+6
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Merge pull request #788 from whitequark/masterClifford Wolf2019-01-151-5/+17
|\ | | | | Document $tribuf and some gates
| * manual: document some gates.whitequark2019-01-141-9/+11
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| * manual: explain $tribuf cell.whitequark2019-01-141-0/+10
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* | Merge pull request #787 from whitequark/flowmap_relaxClifford Wolf2019-01-157-35/+776
|\ \ | |/ |/| flowmap: implement depth relaxation
| * flowmap: clean up terminology.whitequark2019-01-081-17/+18
| | | | | | | | | | | | | | | | | | | | * "map": group gates into LUTs; * "pack": replace gates with LUTs. This is important because we have FlowMap and DF-Map, and currently our messages are ambiguous. Also clean up some other log messages while we're at it.
| * flowmap: implement depth relaxation.whitequark2019-01-087-22/+762
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