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| * | | | | | | | | | | | BRAM improvementsDavid Shah2018-10-121-11/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
| * | | | | | | | | | | | ecp5: Adding BRAM maps for all size optionsDavid Shah2018-10-101-1/+64
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
| * | | | | | | | | | | | ecp5: First BRAM type maps successfullyDavid Shah2018-10-108-10/+76
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
| * | | | | | | | | | | | ecp5: Script for BRAM IO connectionsDavid Shah2018-10-104-64/+115
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
| * | | | | | | | | | | | ecp5: Adding BRAM initialisation and configDavid Shah2018-10-095-0/+73
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
| * | | | | | | | | | | | ecp5: Add blackbox for DP16KDDavid Shah2018-10-051-0/+93
| | |_|_|/ / / / / / / / | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | | | | | | | | | | | Merge pull request #641 from tklam/masterClifford Wolf2018-10-171-0/+69
|\ \ \ \ \ \ \ \ \ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | Fix issue #639
| * | | | | | | | | | | | stop check_signal_in_fanout from traversing FFstklam2018-10-131-2/+2
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| * | | | | | | | | | | | stop check_signal_in_fanout from traversing FFstklam2018-10-131-1/+12
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| * | | | | | | | | | | | Merge branch 'master' of https://github.com/YosysHQ/yosystklam2018-10-136-17/+61
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| * | | | | | | | | | | | Merge branch 'master' of https://github.com/YosysHQ/yosystklam2018-10-034-7/+12
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| * | | | | | | | | | | | | fix bug: pass by referencetklam2018-09-261-1/+1
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| * | | | | | | | | | | | | Fix issue #639TK Lam2018-09-261-0/+58
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* | | | | | | | | | | | | | Merge pull request #638 from udif/pr_reg_wire_errorClifford Wolf2018-10-171-0/+12
|\ \ \ \ \ \ \ \ \ \ \ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix issue #630
| * | | | | | | | | | | | | | Fixed issue #630 by fixing a minor typo in the previous commitUdi Finkelstein2018-09-251-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | (as well as a non critical minor code optimization)
| * | | | | | | | | | | | | | Merge branch 'master' into pr_reg_wire_errorUdi Finkelstein2018-09-18226-1397/+5434
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| * | | | | | | | | | | | | | Fixed remaining cases where we check fo wire reg/wire incorrect assignmentsUdi Finkelstein2018-09-181-0/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | on Yosys-generated assignments. In this case, offending code was: module top(input in, output out); function func; input arg; func = arg; endfunction assign out = func(in); endmodule
* | | | | | | | | | | | | | | We have 2018 nowClifford Wolf2018-10-162-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | | | | | | | | | | | | | | After release is before releaseClifford Wolf2018-10-162-1/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | | | | | | | | | | | | | | Merge branch 'yosys-0.8-rc'Clifford Wolf2018-10-162-141/+1201
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| * | | | | | | | | | | | | | Yosys 0.8Clifford Wolf2018-10-161-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | | | | | | | | | | | | | Update command reference manualClifford Wolf2018-10-161-140/+1200
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | | | | | | | | | | | | | | Improve Verific importer blackbox handlingClifford Wolf2018-10-071-2/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | | | | | | | | | | | | | | Merge pull request #651 from ARandomOWL/stdcells_fixClifford Wolf2018-10-051-1/+1
|\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix IdString M in setup_stdcells()
| * | | | | | | | | | | | | | | Fix IdString M in setup_stdcells()Adrian Wheeldon2018-10-041-1/+1
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* | | | | | | | | | | | | | | Add "write_edif -attrprop"Clifford Wolf2018-10-051-11/+28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | | | | | | | | | | | | | | Merge pull request #654 from mithro/patch-1Clifford Wolf2018-10-051-1/+1
|\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix misspelling in issue_template.md
| * | | | | | | | | | | | | | | Fix misspelling in issue_template.mdTim Ansell2018-10-041-1/+1
| | |_|_|_|_|/ / / / / / / / / | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | It's been bugging me :-P
* / | | | | | | | | | | | | | Fix compiler warning in verific.ccClifford Wolf2018-10-051-0/+2
|/ / / / / / / / / / / / / / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | | | | | | | | | | | | | Add inout ports to cells_xtra.vClifford Wolf2018-10-042-2/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | | | | | | | | | | | | | Merge pull request #650 from mithro/patch-1Clifford Wolf2018-10-041-0/+1
|\ \ \ \ \ \ \ \ \ \ \ \ \ \ | |_|_|_|_|/ / / / / / / / / |/| | | | | | | | | | | | | xilinx: Adding missing inout IO port to IOBUF
| * | | | | | | | | | | | | xilinx: Adding missing inout IO port to IOBUFTim Ansell2018-10-031-0/+1
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* | | | | | | | | | | | | Merge pull request #645 from daveshah1/ecp5_dram_fixClifford Wolf2018-10-021-0/+1
|\ \ \ \ \ \ \ \ \ \ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | ecp5: Don't map ROMs to DRAM
| * | | | | | | | | | | | | ecp5: Don't map ROMs to DRAMDavid Shah2018-10-011-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: David Shah <davey1576@gmail.com>
* | | | | | | | | | | | | | Merge pull request #646 from tomverbeure/issue594Clifford Wolf2018-10-021-1/+2
|\ \ \ \ \ \ \ \ \ \ \ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix for issue 594.
| * | | | | | | | | | | | | | Fix for issue 594.Tom Verbeure2018-10-021-1/+2
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* | | | | | | / / / / / / / Add read_verilog $changed supportDan Gisselquist2018-10-011-1/+4
| |_|_|_|_|_|/ / / / / / / |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | | | | | | | | | | | | Merge branch 'yosys-0.8-rc' of github.com:YosysHQ/yosysClifford Wolf2018-09-301-1/+1
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| * | | | | | | | | | | | Fix handling of $past 2nd argument in read_verilogClifford Wolf2018-09-301-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | | | | | | | | | | | | Merge branch 'yosys-0.8-rc' of github.com:YosysHQ/yosysClifford Wolf2018-09-281-4/+4
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| * | | | | | | | | | | Update to v2 YosysVS templateClifford Wolf2018-09-281-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | | | | | | | | | | | Add "read_verilog -noassert -noassume -assert-assumes"Clifford Wolf2018-09-243-6/+49
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | | | | | | | | | | | Added support for ommited "parameter" in Verilog-2001 style parameter decl ↵Clifford Wolf2018-09-231-3/+9
|/ / / / / / / / / / / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | in SV mode Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | | | | | | | | | | Merge branch 'master' of https://github.com/mmicko/yosys into yosys-0.8-rcClifford Wolf2018-09-231-11/+11
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| * | | | | | | | | | | added prefix to FDirection constants, fixing windows buildMiodrag Milanovic2018-09-211-11/+11
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* | | | | | | | | | | | Update CHANGELOGClifford Wolf2018-09-231-2/+35
|/ / / / / / / / / / / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | | | | | | | | | | Update CHANGLELOGClifford Wolf2018-09-211-5/+27
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | | | | | | | | | | Update ChangelogClifford Wolf2018-09-211-1/+54
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | | | | | | | | | | Merge pull request #633 from mmicko/masterClifford Wolf2018-09-193-1/+14
|\ \ \ \ \ \ \ \ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | Fix Cygwin build and document needed packages
| * | | | | | | | | | | Fix Cygwin build and document needed packagesMiodrag Milanovic2018-09-193-1/+14
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