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	Commit message (Expand)	Author	Age	Files	Lines
*	Merge pull request #591 from hzeller/virtual-override	Clifford Wolf	2018-08-15	1	-4/+4
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\| *	Consistent use of 'override' for virtual methods in derived classes.	Henner Zeller	2018-07-20	1	-4/+4
* \|	Fix use of signed integers in JSON back-end	Clifford Wolf	2018-08-14	1	-1/+3
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*	Add attributes and parameter support to JSON front-end	Clifford Wolf	2017-07-10	1	-0/+2
*	Improved write_json help message	Clifford Wolf	2016-12-29	1	-0/+4
*	write_json: also write module attributes.	whitequark	2016-07-12	1	-2/+6
*	Added "yosys -D" feature	Clifford Wolf	2016-04-21	1	-1/+1
*	user-facing spelling fixes	Sebastian Kuzminsky	2016-02-28	1	-3/+3
*	Another block of spelling fixes	Larry Doolittle	2015-08-14	1	-1/+1
*	Fixed trailing whitespaces	Clifford Wolf	2015-07-02	1	-2/+2
*	Improvements in cellaigs.cc and "json -aig"	Clifford Wolf	2015-06-11	1	-6/+63
*	AigMaker refactoring	Clifford Wolf	2015-06-10	1	-1/+1
*	Added "json -aig"	Clifford Wolf	2015-06-10	1	-9/+63
*	Added "port_directions" to write_json output	Clifford Wolf	2015-04-06	1	-0/+20
*	Documentation for JSON format, added attributes	Clifford Wolf	2015-03-06	1	-16/+156
*	Json bugfix	Clifford Wolf	2015-03-03	1	-1/+1
*	Json backend improvements	Clifford Wolf	2015-03-03	1	-4/+12
*	Added JSON backend	Clifford Wolf	2015-03-02	1	-0/+259

-- // Design Name : parallel_crc_ccitt // File Name : parallel_crc.v // Function : CCITT Parallel CRC // Coder : Deepak Kumar Tala //----------------------------------------------------- module parallel_crc_ccitt ( clk , reset , enable , init , data_in , crc_out ); //-----------Input Ports--------------- input clk ; input reset ; input enable ; input init ; input [7:0] data_in ; //-----------Output Ports--------------- output [15:0] crc_out; //------------Internal Variables-------- reg [15:0] crc_reg; wire [15:0] next_crc; //-------------Code Start----------------- assign crc_out = crc_reg; // CRC Control logic always @ (posedge clk) if (reset) begin crc_reg <= 16'hFFFF; end else if (enable) begin if (init) begin crc_reg <= 16'hFFFF; end else begin crc_reg <= next_crc; end end // Parallel CRC calculation assign next_crc[0] = data_in[7] ^ data_in[0] ^ crc_reg[4] ^ crc_reg[11]; assign next_crc[1] = data_in[1] ^ crc_reg[5]; assign next_crc[2] = data_in[2] ^ crc_reg[6]; assign next_crc[3] = data_in[3] ^ crc_reg[7]; assign next_crc[4] = data_in[4] ^ crc_reg[8]; assign next_crc[5] = data_in[7] ^ data_in[5] ^ data_in[0] ^ crc_reg[4] ^ crc_reg[9] ^ crc_reg[11]; assign next_crc[6] = data_in[6] ^ data_in[1] ^ crc_reg[5] ^ crc_reg[10]; assign next_crc[7] = data_in[7] ^ data_in[2] ^ crc_reg[6] ^ crc_reg[11]; assign next_crc[8] = data_in[3] ^ crc_reg[0] ^ crc_reg[7]; assign next_crc[9] = data_in[4] ^ crc_reg[1] ^ crc_reg[8]; assign next_crc[10] = data_in[5] ^ crc_reg[2] ^ crc_reg[9]; assign next_crc[11] = data_in[6] ^ crc_reg[3] ^ crc_reg[10]; endmodule