| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | Avoid verilog-2k in verilog backend | Clifford Wolf | 2013-03-21 | 1 | -0/+17 |
| * | More support code for $sr cells | Clifford Wolf | 2013-03-14 | 1 | -1/+29 |
| * | Fixed a gcc compiler warning [-Wparentheses] | Clifford Wolf | 2013-03-03 | 1 | -1/+2 |
| * | Added more help messages | Clifford Wolf | 2013-03-01 | 1 | -1/+25 |
| * | initial import | Clifford Wolf | 2013-01-05 | 1 | -0/+905 |
 |
index : iCE40/yosys | |
| [no description] |
| aboutsummaryrefslogtreecommitdiffstats |