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| * Reduce amount of trailing whitespace in code baseLarry Doolittle2019-02-281-3/+3
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| * Merge pull request #827 from ucb-bar/firrtlfixesClifford Wolf2019-02-281-8/+20
| |\ | | | | | | Fix FIRRTL to Verilog process instance subfield assignment.
| | * Fix FIRRTL to Verilog process instance subfield assignment.Jim Lawson2019-02-251-8/+20
| | | | | | | | | | | | | | | | | | Don't emit subfield assignments: bits(x, y, z) <= ... - but instead, add them to the reverse-wire-map where they'll be treated at the end of the module. Enable tests which were disabled due to incorrect treatment of subfields. Assume the `$firrtl2verilog` variable contains any additional switches to control verilog generation (i.e. `--no-dedup -X mverilog`)
| * | Fix smt2 code generation for partially initialized memowy words, fixes #831Clifford Wolf2019-02-281-4/+11
| |/ | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | write_xaiger to behave for undriven/unused inoutsEddie Hung2019-02-261-23/+25
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* | write_xaiger duplicate inout port into out port with $inout.out suffixEddie Hung2019-02-251-3/+26
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* | Cleanup abc9 codeEddie Hung2019-02-251-13/+8
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* | write_xaiger to write __dummy_o__ for -symbols tooEddie Hung2019-02-211-12/+11
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* | Add attributionEddie Hung2019-02-211-0/+1
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* | write_xaiger to use original bit for co, not sigmap()-ed bitEddie Hung2019-02-211-3/+6
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* | Remove swap fileEddie Hung2019-02-201-0/+0
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* | write_aiger: fix CI/CO and symbolsEddie Hung2019-02-202-7/+13
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* | write_xaiger to not write latches, CO/PO fixesEddie Hung2019-02-201-17/+26
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* | Merge branch 'master' into xaigEddie Hung2019-02-192-66/+218
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| * Instead of INIT param on cells, use initial statement with hier ref asEddie Hung2019-02-171-18/+13
| | | | | | | | per @cliffordwolf
| * Merge https://github.com/YosysHQ/yosys into dff_initEddie Hung2019-02-172-86/+246
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| | * Removed unused variables, functions.Jim Lawson2019-02-151-20/+0
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| | * Update cells supported for verilog to FIRRTL conversion.Jim Lawson2019-02-151-48/+225
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Issue warning messages for missing parameterized modules and attempts to set initial values. Replace simple "if (cell-type)" with "else if" chain. Fix FIRRTL shift handling. Add support for parameterized modules, $shift, $shiftx. Handle default output file. Deal with no top module. Automatically run pmuxtree pass. Allow EXTRA_FLAGS and SEED parameters to be set in the environment for tests/tools/autotest.mk. Support FIRRTL regression testing in tests/tools/autotest.sh Add xfirrtl files to test directories to exclude files from FIRRTL regression tests that are known to fail.
* | | CleanupEddie Hung2019-02-161-4/+5
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* | | CleanupEddie Hung2019-02-161-2/+1
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* | | write_xaiger to support non-bit cell connections, and cope with COs for -OEddie Hung2019-02-161-13/+15
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* | | write_aiger -O to write dummy output as __dummy_o__Eddie Hung2019-02-161-2/+5
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* | | Tidy up write_xaigerEddie Hung2019-02-161-8/+6
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* | | write_aiger() to perform CI/CO post-processing and fix symbolsEddie Hung2019-02-161-7/+17
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* | | Fixes needed for DFF circuitsEddie Hung2019-02-151-4/+3
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* | | write_xaiger to cope with unknown cells by transforming them to CI/COEddie Hung2019-02-151-6/+44
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* | | More cleanupEddie Hung2019-02-141-15/+6
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* | | More cleanup of write_xaigerEddie Hung2019-02-141-73/+1
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* | | Get rid of formal stuff from xaiger backendEddie Hung2019-02-141-58/+0
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* | | Merge remote-tracking branch 'origin/read_aiger' into xaigEddie Hung2019-02-131-1/+1
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| * | Remove check for cell->name[0] == '$'Eddie Hung2019-02-061-1/+1
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* | | Merge https://github.com/YosysHQ/yosys into xaigEddie Hung2019-02-131-38/+41
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| * | Merge pull request #802 from whitequark/write_verilog_async_mem_portsClifford Wolf2019-02-121-38/+41
| |\ \ | | | | | | | | write_verilog: correctly emit asynchronous transparent ports
| | * | write_verilog: correctly emit asynchronous transparent ports.whitequark2019-01-291-38/+41
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This commit fixes two related issues: * For asynchronous ports, clock is no longer added to domain list. (This would lead to absurd constructs like `always @(posedge 0)`. * The logic to distinguish synchronous and asynchronous ports is changed to correctly use or avoid clock in all cases. Before this commit, the following RTLIL snippet (after memory_collect) cell $memrd $2 parameter \MEMID "\\mem" parameter \ABITS 2 parameter \WIDTH 4 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 1 parameter \TRANSPARENT 1 connect \CLK 1'0 connect \EN 1'1 connect \ADDR \mem_r_addr connect \DATA \mem_r_data end would lead to invalid Verilog: reg [1:0] _0_; always @(posedge 1'h0) begin _0_ <= mem_r_addr; end assign mem_r_data = mem[_0_]; Note that there are two potential pitfalls remaining after this change: * For asynchronous ports, the \EN input and \TRANSPARENT parameter are silently ignored. (Per discussion in #760 this is the correct behavior.) * For synchronous transparent ports, the \EN input is ignored. This matches the behavior of the $mem simulation cell. Again, see #760.
* | | | Add write_xaigerEddie Hung2019-02-112-21/+11
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* | | | Copy backends/aiger/aiger.cc to xaiger.ccEddie Hung2019-02-081-0/+788
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* | | RefactorEddie Hung2019-02-061-21/+5
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* | | write_verilog to cope with init attr on q when -noexprEddie Hung2019-02-061-2/+32
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* / Add missing blackslash-to-slash convertion to smtio.py (matching ↵Clifford Wolf2019-02-061-1/+1
|/ | | | | | Smt2Worker::get_id() behavior) Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Merge pull request #800 from whitequark/write_verilog_tribufClifford Wolf2019-01-271-0/+12
|\ | | | | write_verilog: write $tribuf cell as ternary
| * write_verilog: write $tribuf cell as ternary.whitequark2019-01-271-0/+12
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* | write_verilog: escape names that match SystemVerilog keywords.whitequark2019-01-271-0/+27
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* Add "write_edif -gndvccy"Clifford Wolf2019-01-171-5/+13
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Fix handling of $shiftx in Verilog back-endClifford Wolf2019-01-151-3/+6
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Fix typographical and grammatical errors and inconsistencies.whitequark2019-01-024-7/+7
| | | | | | | | | | | | The initial list of hits was generated with the codespell command below, and each hit was evaluated and fixed manually while taking context into consideration. DIRS="kernel/ frontends/ backends/ passes/ techlibs/" DIRS="${DIRS} libs/ezsat/ libs/subcircuit" codespell $DIRS -S *.o -L upto,iff,thru,synopsys,uint More hits were found by looking through comments and strings manually.
* Squelch a little more trailing whitespaceLarry Doolittle2018-12-291-3/+3
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* Minor style fixesClifford Wolf2018-12-182-1/+1
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Add btor ops for $mul, $div, $mod and $concatmakaimann2018-12-172-2/+38
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* write_verilog: handle the $shift cell.whitequark2018-12-161-0/+29
| | | | | | | | | | | | | | | | | | | | | | | | | | | The implementation corresponds to the following Verilog, which is lifted straight from simlib.v: module \\$shift (A, B, Y); parameter A_SIGNED = 0; parameter B_SIGNED = 0; parameter A_WIDTH = 0; parameter B_WIDTH = 0; parameter Y_WIDTH = 0; input [A_WIDTH-1:0] A; input [B_WIDTH-1:0] B; output [Y_WIDTH-1:0] Y; generate if (B_SIGNED) begin:BLOCK1 assign Y = $signed(B) < 0 ? A << -B : A >> B; end else begin:BLOCK2 assign Y = A >> B; end endgenerate endmodule
* Merge pull request #736 from whitequark/select_assert_listClifford Wolf2018-12-161-1/+1
|\ | | | | select: print selection if a -assert-* flag causes an error
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