| Commit message (Collapse) | Author | Age | Files | Lines | ||
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| | * | | Fix smt2 code generation for partially initialized memowy words, fixes #831 | Clifford Wolf | 2019-02-28 | 1 | -4/+11 | |
| | |/ | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | | write_xaiger to behave for undriven/unused inouts | Eddie Hung | 2019-02-26 | 1 | -23/+25 | |
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| * | | write_xaiger duplicate inout port into out port with $inout.out suffix | Eddie Hung | 2019-02-25 | 1 | -3/+26 | |
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| * | | Cleanup abc9 code | Eddie Hung | 2019-02-25 | 1 | -13/+8 | |
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| * | | write_xaiger to write __dummy_o__ for -symbols too | Eddie Hung | 2019-02-21 | 1 | -12/+11 | |
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| * | | Add attribution | Eddie Hung | 2019-02-21 | 1 | -0/+1 | |
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| * | | write_xaiger to use original bit for co, not sigmap()-ed bit | Eddie Hung | 2019-02-21 | 1 | -3/+6 | |
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| * | | Remove swap file | Eddie Hung | 2019-02-20 | 1 | -0/+0 | |
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| * | | write_aiger: fix CI/CO and symbols | Eddie Hung | 2019-02-20 | 2 | -7/+13 | |
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| * | | write_xaiger to not write latches, CO/PO fixes | Eddie Hung | 2019-02-20 | 1 | -17/+26 | |
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| * | | Merge branch 'master' into xaig | Eddie Hung | 2019-02-19 | 2 | -66/+218 | |
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| | * | Instead of INIT param on cells, use initial statement with hier ref as | Eddie Hung | 2019-02-17 | 1 | -18/+13 | |
| | | | | | | | | | per @cliffordwolf | |||||
| | * | Merge https://github.com/YosysHQ/yosys into dff_init | Eddie Hung | 2019-02-17 | 2 | -86/+246 | |
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| | | * | Removed unused variables, functions. | Jim Lawson | 2019-02-15 | 1 | -20/+0 | |
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| | | * | Update cells supported for verilog to FIRRTL conversion. | Jim Lawson | 2019-02-15 | 1 | -48/+225 | |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Issue warning messages for missing parameterized modules and attempts to set initial values. Replace simple "if (cell-type)" with "else if" chain. Fix FIRRTL shift handling. Add support for parameterized modules, $shift, $shiftx. Handle default output file. Deal with no top module. Automatically run pmuxtree pass. Allow EXTRA_FLAGS and SEED parameters to be set in the environment for tests/tools/autotest.mk. Support FIRRTL regression testing in tests/tools/autotest.sh Add xfirrtl files to test directories to exclude files from FIRRTL regression tests that are known to fail. | |||||
| * | | | Cleanup | Eddie Hung | 2019-02-16 | 1 | -4/+5 | |
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| * | | | Cleanup | Eddie Hung | 2019-02-16 | 1 | -2/+1 | |
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| * | | | write_xaiger to support non-bit cell connections, and cope with COs for -O | Eddie Hung | 2019-02-16 | 1 | -13/+15 | |
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| * | | | write_aiger -O to write dummy output as __dummy_o__ | Eddie Hung | 2019-02-16 | 1 | -2/+5 | |
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| * | | | Tidy up write_xaiger | Eddie Hung | 2019-02-16 | 1 | -8/+6 | |
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| * | | | write_aiger() to perform CI/CO post-processing and fix symbols | Eddie Hung | 2019-02-16 | 1 | -7/+17 | |
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| * | | | Fixes needed for DFF circuits | Eddie Hung | 2019-02-15 | 1 | -4/+3 | |
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| * | | | write_xaiger to cope with unknown cells by transforming them to CI/CO | Eddie Hung | 2019-02-15 | 1 | -6/+44 | |
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| * | | | More cleanup | Eddie Hung | 2019-02-14 | 1 | -15/+6 | |
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| * | | | More cleanup of write_xaiger | Eddie Hung | 2019-02-14 | 1 | -73/+1 | |
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| * | | | Get rid of formal stuff from xaiger backend | Eddie Hung | 2019-02-14 | 1 | -58/+0 | |
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| * | | | Merge remote-tracking branch 'origin/read_aiger' into xaig | Eddie Hung | 2019-02-13 | 1 | -1/+1 | |
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| | * | | Remove check for cell->name[0] == '$' | Eddie Hung | 2019-02-06 | 1 | -1/+1 | |
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| * | | | Merge https://github.com/YosysHQ/yosys into xaig | Eddie Hung | 2019-02-13 | 1 | -38/+41 | |
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| | * | | Merge pull request #802 from whitequark/write_verilog_async_mem_ports | Clifford Wolf | 2019-02-12 | 1 | -38/+41 | |
| | |\ \ | | | | | | | | | write_verilog: correctly emit asynchronous transparent ports | |||||
| | | * | | write_verilog: correctly emit asynchronous transparent ports. | whitequark | 2019-01-29 | 1 | -38/+41 | |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This commit fixes two related issues: * For asynchronous ports, clock is no longer added to domain list. (This would lead to absurd constructs like `always @(posedge 0)`. * The logic to distinguish synchronous and asynchronous ports is changed to correctly use or avoid clock in all cases. Before this commit, the following RTLIL snippet (after memory_collect) cell $memrd $2 parameter \MEMID "\\mem" parameter \ABITS 2 parameter \WIDTH 4 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 1 parameter \TRANSPARENT 1 connect \CLK 1'0 connect \EN 1'1 connect \ADDR \mem_r_addr connect \DATA \mem_r_data end would lead to invalid Verilog: reg [1:0] _0_; always @(posedge 1'h0) begin _0_ <= mem_r_addr; end assign mem_r_data = mem[_0_]; Note that there are two potential pitfalls remaining after this change: * For asynchronous ports, the \EN input and \TRANSPARENT parameter are silently ignored. (Per discussion in #760 this is the correct behavior.) * For synchronous transparent ports, the \EN input is ignored. This matches the behavior of the $mem simulation cell. Again, see #760. | |||||
| * | | | | Add write_xaiger | Eddie Hung | 2019-02-11 | 2 | -21/+11 | |
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| * | | | | Copy backends/aiger/aiger.cc to xaiger.cc | Eddie Hung | 2019-02-08 | 1 | -0/+788 | |
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| * | | | Refactor | Eddie Hung | 2019-02-06 | 1 | -21/+5 | |
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| * | | | write_verilog to cope with init attr on q when -noexpr | Eddie Hung | 2019-02-06 | 1 | -2/+32 | |
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| * / | Add missing blackslash-to-slash convertion to smtio.py (matching ↵ | Clifford Wolf | 2019-02-06 | 1 | -1/+1 | |
| |/ | | | | | | Smt2Worker::get_id() behavior) Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | Merge pull request #800 from whitequark/write_verilog_tribuf | Clifford Wolf | 2019-01-27 | 1 | -0/+12 | |
| |\ | | | | | write_verilog: write $tribuf cell as ternary | |||||
| | * | write_verilog: write $tribuf cell as ternary. | whitequark | 2019-01-27 | 1 | -0/+12 | |
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| * | | write_verilog: escape names that match SystemVerilog keywords. | whitequark | 2019-01-27 | 1 | -0/+27 | |
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| * | Add "write_edif -gndvccy" | Clifford Wolf | 2019-01-17 | 1 | -5/+13 | |
| | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | Fix handling of $shiftx in Verilog back-end | Clifford Wolf | 2019-01-15 | 1 | -3/+6 | |
| | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | Fix typographical and grammatical errors and inconsistencies. | whitequark | 2019-01-02 | 4 | -7/+7 | |
| | | | | | | | | | | | | | The initial list of hits was generated with the codespell command below, and each hit was evaluated and fixed manually while taking context into consideration. DIRS="kernel/ frontends/ backends/ passes/ techlibs/" DIRS="${DIRS} libs/ezsat/ libs/subcircuit" codespell $DIRS -S *.o -L upto,iff,thru,synopsys,uint More hits were found by looking through comments and strings manually. | |||||
| * | Squelch a little more trailing whitespace | Larry Doolittle | 2018-12-29 | 1 | -3/+3 | |
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| * | Minor style fixes | Clifford Wolf | 2018-12-18 | 2 | -1/+1 | |
| | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | Add btor ops for $mul, $div, $mod and $concat | makaimann | 2018-12-17 | 2 | -2/+38 | |
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| * | write_verilog: handle the $shift cell. | whitequark | 2018-12-16 | 1 | -0/+29 | |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | The implementation corresponds to the following Verilog, which is lifted straight from simlib.v: module \\$shift (A, B, Y); parameter A_SIGNED = 0; parameter B_SIGNED = 0; parameter A_WIDTH = 0; parameter B_WIDTH = 0; parameter Y_WIDTH = 0; input [A_WIDTH-1:0] A; input [B_WIDTH-1:0] B; output [Y_WIDTH-1:0] Y; generate if (B_SIGNED) begin:BLOCK1 assign Y = $signed(B) < 0 ? A << -B : A >> B; end else begin:BLOCK2 assign Y = A >> B; end endgenerate endmodule | |||||
| * | Merge pull request #736 from whitequark/select_assert_list | Clifford Wolf | 2018-12-16 | 1 | -1/+1 | |
| |\ | | | | | select: print selection if a -assert-* flag causes an error | |||||
| | * | write_verilog: add a missing newline. | whitequark | 2018-12-16 | 1 | -1/+1 | |
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| * | | Merge pull request #729 from whitequark/write_verilog_initial | Clifford Wolf | 2018-12-16 | 1 | -0/+2 | |
| |\ \ | | | | | | | write_verilog: correctly map RTLIL `sync init` | |||||
| | * | | write_verilog: correctly map RTLIL `sync init`. | whitequark | 2018-12-07 | 1 | -0/+2 | |
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index : iCE40/yosys | |
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