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* | Merge pull request #1797 from epfl-vlsc/firrtl_backend_fileinfoClaire Wolf2020-04-161-29/+51
|\ \ | |/ |/| Keep file information when emitting firrtl
| * Fix indentationSahand Kashani2020-04-091-3/+3
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| * Remove dependency on ilang backend since we no longer use itSahand Kashani2020-04-081-1/+0
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| * Merge branch 'master' of github.com:YosysHQ/yosys into firrtl_backend_fileinfoSahand Kashani2020-04-0814-1131/+1243
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| * | Remove unnecessary pruning of double-quotingSahand Kashani2020-04-081-5/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In the past I was calling the ILANG_BACKEND::dump_const() to dump values to an output stream. When these values were strings, the function used to add quotes around them. The firrtl compiler, in turn, escaped these quotes and the result was double-quoted strings which were hard to read. However I'm now calling design_entity->get_src_attribute() directly and there is no additional quote being put around it, so we can safely remove the unnecessary call to str.erase() here.
| * | Remove use of auto for simple types + simplify src attribute computationSahand Kashani2020-03-241-10/+5
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| * | Refactor to directly call ILANG_BACKEND::dump_const() + directly lookup src ↵Sahand Kashani2020-03-241-68/+15
| | | | | | | | | | | | attribute
| * | Indentation conventionsSahand Kashani2020-03-231-5/+6
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| * | Const parameter in function (backends/firrtl/firrtl.cc)Sahand Kashani-Akhavan2020-03-231-1/+1
| | | | | | | | | Co-Authored-By: Alberto Gonzalez <61295559+boqwxp@users.noreply.github.com>
| * | Strip quotes around fileinfo stringsSahand Kashani2020-03-211-1/+5
| | | | | | | | | | | | | | | | | | Yosys puts quotes around the string that represents the fileinfo whereas firrtl does not. So when firrtl sees quotes, it escapes them with an extra backslash which makes it hard to read afterwards.
| * | Add fileinfo to firrtl backend for assignments and non-instance cellsSahand Kashani2020-03-211-21/+30
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| * | Refactor fileinfo emission characters to single locationSahand Kashani2020-03-201-6/+8
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| * | Add fileinfo to firrtl backend for instancesSahand Kashani2020-03-191-2/+3
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| * | Add fileinfo to firrtl backend for modules and wiresSahand Kashani2020-03-191-12/+20
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| * | Add fileinfo to firrtl backend for top-level circuitSahand Kashani2020-03-191-1/+62
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* | | Merge pull request #1830 from boqwxp/qbfsatN. Engelhardt2020-04-151-3/+15
|\ \ \ | | | | | | | | Add `qbfsat` command to integrate exists-forall solving and specialization
| * | | Updated `yosys-smtbmc` to optionally dump raw bit strings, and fixed hole ↵Alberto Gonzalez2020-04-041-3/+15
| | | | | | | | | | | | | | | | value recovery using that mode.
* | | | json: Update format documentation.Marcelina Kościelnicka2020-04-151-12/+32
| | | | | | | | | | | | | | | | Fixes #1693.
* | | | cxxrtl: Fix handling of unclocked memory read portsDavid Shah2020-04-141-2/+3
| | | | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | | | Merge pull request #1922 from whitequark/write_cxxrtl-disconnected-outputswhitequark2020-04-141-0/+2
|\ \ \ \ | | | | | | | | | | write_cxxrtl: ignore disconnected module ports
| * | | | write_cxxrtl: ignore disconnected module ports.whitequark2020-04-141-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | E.g. port `q` in `submod x(.p(p), .q());`. Fixes #1920.
* | | | | Merge pull request #1921 from whitequark/write_cxxrtl-separate-compilationwhitequark2020-04-142-10/+82
|\ \ \ \ \ | | | | | | | | | | | | write_cxxrtl: enable separate compilation
| * | | | | write_verilog: fix precondition check.whitequark2020-04-141-1/+1
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| * | | | | write_cxxrtl: enable separate compilation.whitequark2020-04-141-9/+81
| |/ / / / | | | | | | | | | | | | | | | | | | | | | | | | | This commit makes it possible to use several cxxrtl-generated files in one application, as well as compiling cxxrtl-generated code as a separate compilation unit.
* / / / / xaiger: add check for $__ABC9_DELAY modelEddie Hung2020-04-131-0/+4
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* | | | Support custom PROGRAM_PREFIXMiodrag Milanovic2020-04-102-9/+8
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* | | | write_cxxrtl: add basic documentation.whitequark2020-04-091-1/+16
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* | | | write_cxxrtl: add support for $dlatch and $dlatchsr cells.whitequark2020-04-091-3/+16
| | | | | | | | | | | | | | | | Also, fix codegen for $dffe and $adff.
* | | | write_cxxrtl: add support for $sr cell.whitequark2020-04-091-27/+35
| | | | | | | | | | | | | | | | | | | | | | | | Also, fix the semantics of SET/CLR inputs of the $dffsr cell, and fix the scheduling of async FF cells to consider ARST/SET/CLR->Q as a forward combinatorial arc.
* | | | write_cxxrtl: add support for $slice and $concat cells.whitequark2020-04-091-1/+16
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* | | | write_cxxrtl: improve writable memory handling.whitequark2020-04-092-65/+87
| | | | | | | | | | | | | | | | | | | | | | | | This commit reduces space and time overhead for writable memories to O(write port count) in both cases; implements handling for write port priorities; and simplifies runtime representation of memories.
* | | | write_cxxrtl: add support for hierarchical designs.whitequark2020-04-091-18/+107
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Hierarchical design simulations are generally much slower, but this comes with a major increase in flexibility: 1. Since the `flatten` pass currently does not support flattening of designs with processes, this is the only way to simulate such designs with cxxrtl. 2. Support for hierarchy paves way for simulation black boxes, which are necessary for e.g. replacing PHYs with C++ code that integrates with the host system.
* | | | write_cxxrtl: avoid undefined behavior on out-of-bounds memory access.whitequark2020-04-092-46/+78
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | After this commit, if NDEBUG is not defined, out-of-bounds accesses cause assertion failures for reads and writes. If NDEBUG is defined, out-of-bounds reads return zeroes, and out-of-bounds writes are ignored. This commit also adds support for memories that start with a non-zero index (`Memory::start_offset` in RTLIL).
* | | | write_cxxrtl: statically schedule comb logic and localize wires.whitequark2020-04-092-68/+368
| | | | | | | | | | | | | | | | | | | | | | | | This results in further massive gains in performance, modest decrease in compile time, and, for designs without feedback arcs, makes it possible to run eval() once per clock edge in certain conditions.
* | | | write_cxxrtl: elide wires for results of comb cells used once.whitequark2020-04-091-35/+359
| | | | | | | | | | | | | | | | | | | | This results in massive gains in performance, equally massive reduction in compile time, and improved readability.
* | | | write_cxxrtl: new backend.whitequark2020-04-093-0/+2010
| |_|/ |/| | | | | | | | | | | This commit adds a basic implementation that isn't very performant but implements most of the planned features.
* | | kernel: big fat patch to use more ID::*, otherwise ID(*)Eddie Hung2020-04-029-727/+727
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* | | Update backends/btor/btor.cc; credit @boqwxpEddie Hung2020-04-021-2/+1
| | | | | | | | | Co-Authored-By: Alberto Gonzalez <61295559+boqwxp@users.noreply.github.com>
* | | kernel: use more ID::*Eddie Hung2020-04-0211-280/+280
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* | | Merge pull request #1770 from YosysHQ/claire/btor_symbolsClaire Wolf2020-04-021-36/+60
|\ \ \ | | | | | | | | Improve write_btor symbol handling
| * | | Improve write_btor symbol handlingClaire Wolf2020-03-141-36/+60
| | | | | | | | | | | | | | | | Signed-off-by: Claire Wolf <claire@symbioticeda.com>
* | | | Merge pull request #1765 from YosysHQ/claire/btor_infoClaire Wolf2020-04-021-9/+113
|\| | | | | | | | | | | Add info-file and cover features to write_btor
| * | | Add info-file and cover features to write_btorClaire Wolf2020-03-131-9/+113
| | | | | | | | | | | | | | | | Signed-off-by: Claire Wolf <claire@symbioticeda.com>
* | | | Update `RTLIL::id2cstr()` usage to `log_id`.Alberto Gonzalez2020-04-011-2/+2
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* | | | Clean up pseudo-private member usage in `backends/intersynth/intersynth.cc`.Alberto Gonzalez2020-04-011-22/+19
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* | | | Clean up pseudo-private member usage in `backends/blif/blif.cc`.Alberto Gonzalez2020-04-011-15/+11
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* | | | Clean up pseudo-private member usage in `backends/verilog/verilog_backend.cc`.Alberto Gonzalez2020-04-011-22/+19
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* | | | Clean up pseudo-private member usage in `backends/spice/spice.cc`.Alberto Gonzalez2020-04-011-13/+9
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* | | | Clean up pseudo-private member usage in `backends/edif/edif.cc`.Alberto Gonzalez2020-04-011-23/+18
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* | | | Clean up pseudo-private member usage in `backends/ilang/ilang_backend.cc`.Alberto Gonzalez2020-04-011-6/+6
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