| Commit message (Collapse) | Author | Age | Files | Lines | ||
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| | * | Do not sigmap keep bits inside write_xaiger | Eddie Hung | 2019-11-26 | 1 | -1/+1 | |
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| | * | xaiger: do not promote output wires | Eddie Hung | 2019-11-26 | 1 | -5/+0 | |
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| * | | Add "synth_xilinx -dff" option, cleanup abc9 | Eddie Hung | 2019-12-30 | 1 | -2/+3 | |
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| * | | Really fix it! | Eddie Hung | 2019-12-27 | 1 | -10/+7 | |
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| * | | write_xaiger: fix arrival times for non boxes | Eddie Hung | 2019-12-27 | 1 | -18/+25 | |
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| * | | write_xaiger to opt instead of just clean whiteboxes | Eddie Hung | 2019-12-23 | 1 | -1/+1 | |
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| * | | Cleanup xaiger, remove unnecessary complexity with inout | Eddie Hung | 2019-12-17 | 1 | -61/+20 | |
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| * | | Do not sigmap | Eddie Hung | 2019-12-17 | 1 | -1/+1 | |
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| * | | Revert "Use sigmap signal" | Eddie Hung | 2019-12-17 | 1 | -1/+1 | |
| | | | | | | | | | This reverts commit 42f990f3a6b7928841fa0e290fa2688925485907. | |||||
| * | | Use sigmap signal | Eddie Hung | 2019-12-16 | 1 | -1/+1 | |
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| * | | Skip $inout transformation if not a PI | Eddie Hung | 2019-12-16 | 1 | -3/+5 | |
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| * | | Revert "write_xaiger: use sigmap bits more consistently" | Eddie Hung | 2019-12-16 | 1 | -4/+5 | |
| | | | | | | | | | This reverts commit 6c340112fee1bb8989cbd41923aaa627d77d5110. | |||||
| * | | write_xaiger: use sigmap bits more consistently | Eddie Hung | 2019-12-16 | 1 | -5/+4 | |
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| * | | Fix writing non-whole modules, including inouts and keeps | Eddie Hung | 2019-12-06 | 1 | -90/+81 | |
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| * | | write_xaiger to support part-selected modules again | Eddie Hung | 2019-12-05 | 1 | -11/+37 | |
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| * | | Cleanup | Eddie Hung | 2019-12-03 | 1 | -11/+12 | |
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| * | | write_xaiger to consume abc9_init attribute for abc9_flops | Eddie Hung | 2019-12-03 | 1 | -34/+28 | |
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| * | | Add comment, use sigmap | Eddie Hung | 2019-11-27 | 1 | -2/+2 | |
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| * | | Revert "Fold loop" | Eddie Hung | 2019-11-27 | 1 | -3/+6 | |
| | | | | | | | | | This reverts commit da51492dbcc9f19a4808ef18e8ae1222bc55b118. | |||||
| * | | xaiger: do not promote output wires | Eddie Hung | 2019-11-26 | 1 | -5/+0 | |
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| * | | Fold loop | Eddie Hung | 2019-11-25 | 1 | -6/+3 | |
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| * | | Do not sigmap keep bits inside write_xaiger | Eddie Hung | 2019-11-25 | 1 | -1/+1 | |
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| * | | write_xaiger back to working with whole modules only | Eddie Hung | 2019-11-22 | 1 | -5/+2 | |
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| * | | Revert "write_xaiger to not use module POs but only write outputs if driven" | Eddie Hung | 2019-11-22 | 1 | -23/+11 | |
| | | | | | | | | | This reverts commit 0ab1e496dc601f8e9d5efbcc5b2be7cf6b2d9673. | |||||
| * | | write_xaiger to not use module POs but only write outputs if driven | Eddie Hung | 2019-11-21 | 1 | -11/+23 | |
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| * | | abc9 to support async flops $_DFF_[NP][NP][01]_ | Eddie Hung | 2019-11-19 | 1 | -1/+2 | |
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| * | | Merge remote-tracking branch 'origin/master' into xaig_dff | Eddie Hung | 2019-11-19 | 4 | -21/+103 | |
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| | * | write_verilog: add -extmem option, to write split memory init files. | whitequark | 2019-11-18 | 1 | -10/+80 | |
| | | | | | | | | | | | Some toolchains (in particular Quartus) are pathologically slow if a large amount of assignments in `initial` blocks are used. | |||||
| | * | Use cell name for btor bad state props when it is a public name | Clifford Wolf | 2019-11-14 | 1 | -9/+5 | |
| | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| | * | Add an info string symbol for bad states in btor backend | Makai Mann | 2019-11-11 | 1 | -1/+10 | |
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| | * | Fix write_aiger bug added in 524af21 | Clifford Wolf | 2019-11-04 | 1 | -0/+3 | |
| | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| | * | Merge pull request #1393 from whitequark/write_verilog-avoid-init | Clifford Wolf | 2019-10-27 | 1 | -4/+5 | |
| | |\ | | | | | | | write_verilog: do not print (*init*) attributes on regs | |||||
| | | * | write_verilog: do not print (*init*) attributes on regs. | whitequark | 2019-09-22 | 1 | -4/+5 | |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If an init value is emitted for a reg, an (*init*) attribute is never necessary, since it is exactly equivalent. On the other hand, some tools that consume Verilog (ISE, Vivado, Quartus) complain about (*init*) attributes because their interpretation differs from Yosys. All (*init*) attributes that would not become reg init values anyway are emitted as before. | |||||
| | * | | Bugfix in smtio vcd handling of $-identifiers | Clifford Wolf | 2019-10-23 | 1 | -6/+9 | |
| | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | | | Rename $currQ to $abc9_currQ | Eddie Hung | 2019-10-07 | 1 | -8/+8 | |
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| * | | | Get rid of latch_* in write_xaiger | Eddie Hung | 2019-10-07 | 1 | -7/+1 | |
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| * | | | Remove "write_xaiger -zinit" | Eddie Hung | 2019-10-07 | 1 | -16/+6 | |
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| * | | | Add comment on default flop init | Eddie Hung | 2019-10-07 | 1 | -0/+1 | |
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| * | | | Get rid of output_port lookup | Eddie Hung | 2019-10-07 | 1 | -14/+8 | |
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| * | | | Do not require changes to cells_sim.v; try and work out comb model | Eddie Hung | 2019-10-05 | 1 | -48/+70 | |
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| * | | | Error if $currQ not found | Eddie Hung | 2019-10-05 | 1 | -0/+4 | |
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| * | | | Fix merge issues | Eddie Hung | 2019-10-04 | 1 | -1/+1 | |
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| * | | | Merge remote-tracking branch 'origin/eddie/abc_to_abc9' into xaig_dff | Eddie Hung | 2019-10-04 | 1 | -11/+11 | |
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| | * | | Rename abc_* names/attributes to more precisely be abc9_* | Eddie Hung | 2019-10-04 | 1 | -9/+9 | |
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| * | | | Merge remote-tracking branch 'origin/master' into xaig_dff | Eddie Hung | 2019-10-03 | 2 | -20/+23 | |
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| | * | | Change smtbmc "Warmup failed" status to "PREUNSAT" | Clifford Wolf | 2019-10-03 | 1 | -14/+14 | |
| | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| | * | | Fix btor back-end to use "state" instead of "input" for undef init bits | Clifford Wolf | 2019-10-02 | 1 | -6/+9 | |
| | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | | | No need to punch ports at all | Eddie Hung | 2019-09-30 | 1 | -0/+24 | |
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| * | | | Remove need for $currQ port connection | Eddie Hung | 2019-09-30 | 1 | -3/+3 | |
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| * | | | Cleanup | Eddie Hung | 2019-09-30 | 1 | -100/+3 | |
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index : iCE40/yosys | |
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