| Commit message (Collapse) | Author | Age | Files | Lines | ||
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| * | | | Merge remote-tracking branch 'origin/clifford/whitebox' into xaig | Eddie Hung | 2019-04-18 | 8 | -12/+12 | |
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| | * | | Add "whitebox" attribute, add "read_verilog -wb" | Clifford Wolf | 2019-04-18 | 8 | -12/+12 | |
| | |/ | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | | Fix $anyseq warning and cleanup | Eddie Hung | 2019-04-17 | 1 | -16/+7 | |
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| * | | Cope with inout ports | Eddie Hung | 2019-04-17 | 1 | -1/+15 | |
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| * | | Stop topological sort at abc_flop_q | Eddie Hung | 2019-04-17 | 1 | -7/+13 | |
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| * | | Remove init* from xaiger, also topo-sort cells for box flow | Eddie Hung | 2019-04-17 | 1 | -95/+157 | |
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| * | | Optimise | Eddie Hung | 2019-04-16 | 1 | -4/+3 | |
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| * | | CIs before PIs; also sort each cell's connections before iterating | Eddie Hung | 2019-04-16 | 1 | -5/+7 | |
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| * | | Port from xc7mux branch | Eddie Hung | 2019-04-16 | 1 | -37/+109 | |
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| * | | Output __const0__ and __const1__ CIs | Eddie Hung | 2019-04-12 | 1 | -7/+10 | |
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| * | | ci_bits and co_bits now a list, order is important for ABC | Eddie Hung | 2019-04-12 | 1 | -24/+34 | |
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| * | | WIP | Eddie Hung | 2019-04-12 | 1 | -14/+68 | |
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| * | | Add non-input bits driven by unrecognised cells as ci_bits | Eddie Hung | 2019-04-10 | 1 | -1/+1 | |
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| * | | Merge branch 'master' into xaig | Eddie Hung | 2019-04-08 | 9 | -62/+305 | |
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| | * | Refine memory support to deal with general Verilog memory definitions. | Jim Lawson | 2019-04-01 | 1 | -30/+173 | |
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| | * | Add support for memory initialization to write_btor | Clifford Wolf | 2019-03-23 | 1 | -0/+53 | |
| | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| | * | Fix BTOR output tags syntax in writye_btor | Clifford Wolf | 2019-03-23 | 1 | -2/+1 | |
| | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| | * | Fix smtbmc.py handling of zero appended steps | Clifford Wolf | 2019-03-14 | 1 | -5/+5 | |
| | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| | * | Fix a syntax bug in ilang backend related to process case statements | Clifford Wolf | 2019-03-14 | 1 | -1/+1 | |
| | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| | * | Merge pull request #869 from cr1901/win-shell | Clifford Wolf | 2019-03-14 | 1 | -1/+17 | |
| | |\ | | | | | | | Install launcher executable when running yosys-smtbmc on Windows. | |||||
| | | * | Install launcher executable when running yosys-smtbmc on Windows. | William D. Jones | 2019-03-13 | 1 | -1/+17 | |
| | | | | | | | | | | | | | Signed-off-by: William D. Jones <thor0505@comcast.net> | |||||
| | * | | Improve determinism of IdString DB for similar scripts | Clifford Wolf | 2019-03-11 | 1 | -0/+4 | |
| | |/ | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| | * | Fix signed $shift/$shiftx handling in write_smt2 | Clifford Wolf | 2019-03-09 | 1 | -1/+2 | |
| | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| | * | Use SVA label in smt export if available | Clifford Wolf | 2019-03-07 | 1 | -2/+2 | |
| | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| | * | Ensure fid() calls make_id() for consistency; tests/simple/dff_init.v fails | Jim Lawson | 2019-03-04 | 1 | -2/+1 | |
| | | | | | | | | | Mark dff_init.v as expected to fail since it uses "initial value". | |||||
| | * | Fix "write_edif -gndvccy" | Clifford Wolf | 2019-03-01 | 1 | -1/+1 | |
| | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| | * | Add "write_verilog -siminit" | Clifford Wolf | 2019-02-28 | 1 | -2/+11 | |
| | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| | * | Reduce amount of trailing whitespace in code base | Larry Doolittle | 2019-02-28 | 1 | -3/+3 | |
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| | * | Merge pull request #827 from ucb-bar/firrtlfixes | Clifford Wolf | 2019-02-28 | 1 | -8/+20 | |
| | |\ | | | | | | | Fix FIRRTL to Verilog process instance subfield assignment. | |||||
| | | * | Fix FIRRTL to Verilog process instance subfield assignment. | Jim Lawson | 2019-02-25 | 1 | -8/+20 | |
| | | | | | | | | | | | | | | | | | | | Don't emit subfield assignments: bits(x, y, z) <= ... - but instead, add them to the reverse-wire-map where they'll be treated at the end of the module. Enable tests which were disabled due to incorrect treatment of subfields. Assume the `$firrtl2verilog` variable contains any additional switches to control verilog generation (i.e. `--no-dedup -X mverilog`) | |||||
| | * | | Fix smt2 code generation for partially initialized memowy words, fixes #831 | Clifford Wolf | 2019-02-28 | 1 | -4/+11 | |
| | |/ | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | | write_xaiger to behave for undriven/unused inouts | Eddie Hung | 2019-02-26 | 1 | -23/+25 | |
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| * | | write_xaiger duplicate inout port into out port with $inout.out suffix | Eddie Hung | 2019-02-25 | 1 | -3/+26 | |
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| * | | Cleanup abc9 code | Eddie Hung | 2019-02-25 | 1 | -13/+8 | |
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| * | | write_xaiger to write __dummy_o__ for -symbols too | Eddie Hung | 2019-02-21 | 1 | -12/+11 | |
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| * | | Add attribution | Eddie Hung | 2019-02-21 | 1 | -0/+1 | |
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| * | | write_xaiger to use original bit for co, not sigmap()-ed bit | Eddie Hung | 2019-02-21 | 1 | -3/+6 | |
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| * | | Remove swap file | Eddie Hung | 2019-02-20 | 1 | -0/+0 | |
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| * | | write_aiger: fix CI/CO and symbols | Eddie Hung | 2019-02-20 | 2 | -7/+13 | |
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| * | | write_xaiger to not write latches, CO/PO fixes | Eddie Hung | 2019-02-20 | 1 | -17/+26 | |
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| * | | Merge branch 'master' into xaig | Eddie Hung | 2019-02-19 | 2 | -66/+218 | |
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| | * | Instead of INIT param on cells, use initial statement with hier ref as | Eddie Hung | 2019-02-17 | 1 | -18/+13 | |
| | | | | | | | | | per @cliffordwolf | |||||
| | * | Merge https://github.com/YosysHQ/yosys into dff_init | Eddie Hung | 2019-02-17 | 2 | -86/+246 | |
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| | | * | Removed unused variables, functions. | Jim Lawson | 2019-02-15 | 1 | -20/+0 | |
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| | | * | Update cells supported for verilog to FIRRTL conversion. | Jim Lawson | 2019-02-15 | 1 | -48/+225 | |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Issue warning messages for missing parameterized modules and attempts to set initial values. Replace simple "if (cell-type)" with "else if" chain. Fix FIRRTL shift handling. Add support for parameterized modules, $shift, $shiftx. Handle default output file. Deal with no top module. Automatically run pmuxtree pass. Allow EXTRA_FLAGS and SEED parameters to be set in the environment for tests/tools/autotest.mk. Support FIRRTL regression testing in tests/tools/autotest.sh Add xfirrtl files to test directories to exclude files from FIRRTL regression tests that are known to fail. | |||||
| * | | | Cleanup | Eddie Hung | 2019-02-16 | 1 | -4/+5 | |
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| * | | | Cleanup | Eddie Hung | 2019-02-16 | 1 | -2/+1 | |
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| * | | | write_xaiger to support non-bit cell connections, and cope with COs for -O | Eddie Hung | 2019-02-16 | 1 | -13/+15 | |
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| * | | | write_aiger -O to write dummy output as __dummy_o__ | Eddie Hung | 2019-02-16 | 1 | -2/+5 | |
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| * | | | Tidy up write_xaiger | Eddie Hung | 2019-02-16 | 1 | -8/+6 | |
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