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* Support for arrays with swapped ranges within structsDag Lem2022-11-121-1/+1
| | | | | | This also corrects the implementation of C type arrays within structs. Fixes #3550
* verilog: fix const func eval with upto variablesZachary Snow2022-02-111-0/+1
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* verilog: use derived module info to elaborate cell connectionsZachary Snow2021-10-251-2/+12
| | | | | | | | - Attempt to lookup a derived module if it potentially contains a port connection with elaboration ambiguities - Mark the cell if module has not yet been derived - This can be extended to implement automatic hierarchical port connections in a future change
* Split out logic for reprocessing an AstModuleRupert Swarbrick2021-10-251-1/+13
| | | | | This will enable other features to use same core logic for replacing an existing AstModule with a newly elaborated version.
* Generate an RTLIL representation of bind constructsRupert Swarbrick2021-08-131-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | This code now takes the AST nodes of type AST_BIND and generates a representation in the RTLIL for them. This is a little tricky, because a binding of the form: bind baz foo_t foo_i (.arg (1 + bar)); means "make an instance of foo_t called foo_i, instantiate it inside baz and connect the port arg to the result of the expression 1+bar". Of course, 1+bar needs a cell for the addition. Where should that cell live? With this patch, the Binding structure that represents the construct is itself an AST::AstModule module. This lets us put the adder cell inside it. We'll pull the contents out and plonk them into 'baz' when we actually do the binding operation as part of the hierarchy pass. Of course, we don't want RTLIL::Binding to contain an AST::AstModule (since kernel code shouldn't depend on a frontend), so we define RTLIL::Binding as an abstract base class and put the AST-specific code into an AST::Binding subclass. This is analogous to the AST::AstModule class.
* verilog: Emit $meminit_v2 cell.Marcelina Kościelnicka2021-07-281-1/+1
| | | | Fixes #2447.
* Add support for parsing the SystemVerilog 'bind' constructRupert Swarbrick2021-07-161-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This doesn't do anything useful yet: the patch just adds support for the syntax to the lexer and parser and adds some tests to check the syntax parses properly. This generates AST nodes, but doesn't yet generate RTLIL. Since our existing hierarchical_identifier parser doesn't allow bit selects (so you can't do something like foo[1].bar[2].baz), I've also not added support for a trailing bit select (the "constant_bit_select" non-terminal in "bind_target_instance" in the spec). If we turn out to need this in future, we'll want to augment hierarchical_identifier and its other users too. Note that you can't easily use the BNF from the spec: bind_directive ::= "bind" bind_target_scope [ : bind_target_instance_list] bind_instantiation ; | "bind" bind_target_instance bind_instantiation ; even if you fix the lookahead problem, because code like this matches both branches in the BNF: bind a b b_i (.*); The problem is that 'a' could either be a module name or a degenerate hierarchical reference. This seems to be a genuine syntactic ambiguity, which the spec resolves (p739) by saying that we have to wait until resolution time (the hierarchy pass) and take whatever is defined, treating 'a' as an instance name if it names both an instance and a module. To keep the parser simple, it currently accepts this invalid syntax: bind a.b : c d e (.*); This is invalid because we're in the first branch of the BNF above, so the "a.b" term should match bind_target_scope: a module or interface identifier, not an arbitrary hierarchical identifier. This will fail in the hierarchy pass (when it's implemented in a future patch).
* sv: fix two struct access bugsZachary Snow2021-07-151-0/+3
| | | | | - preserve signedness of struct members - fix initial width detection of struct members (e.g., in case expressions)
* Merge pull request #2817 from YosysHQ/claire/fixemailsClaire Xen2021-06-091-1/+1
|\ | | | | Fixing old e-mail addresses and deadnames
| * Fixing old e-mail addresses and deadnamesClaire Xenia Wolf2021-06-081-1/+1
| | | | | | | | | | | | | | | | s/((Claire|Xen|Xenia|Clifford)\s+)+(Wolf|Xen)\s+<(claire|clifford)@(symbioticeda.com|clifford.at|yosyshq.com)>/Claire Xenia Wolf <claire@yosyshq.com>/gi; s/((Nina|Nak|N\.)\s+)+Engelhardt\s+<nak@(symbioticeda.com|yosyshq.com)>/N. Engelhardt <nak@yosyshq.com>/gi; s/((David)\s+)+Shah\s+<(dave|david)@(symbioticeda.com|yosyshq.com|ds0.me)>/David Shah <dave@ds0.me>/gi; s/((Miodrag)\s+)+Milanovic\s+<(miodrag|micko)@(symbioticeda.com|yosyshq.com)>/Miodrag Milanovic <micko@yosyshq.com>/gi; s,https?://www.clifford.at/yosys/,http://yosyshq.net/yosys/,g;
* | verilog: check for module scope identifiers during width detectionZachary Snow2021-06-081-0/+3
|/ | | | | | | | The recent fix for case expression width detection causes the width of the expressions to be queried before they are simplified. Because the logic supporting module scope identifiers only existed in simplify, looking them up would fail during width detection. This moves the logic to a common helper used in both simplify() and detectSignWidthWorker().
* verilog: fix case expression sign and width handlingZachary Snow2021-05-251-1/+1
| | | | | | | | | - The case expression and case item expressions are extended to the maximum width among them, and are only interpreted as signed if all of them are signed - Add overall width and sign detection for AST_CASE - Add sign argument to genWidthRTLIL helper - Coverage for both const and non-const case statements
* Change the type of current_module to ModuleRupert Swarbrick2021-05-131-1/+1
| | | | | | | | | | | The current_module global is needed so that genRTLIL has somewhere to put cells and wires that it generates as it makes sense of expressions that it sees. However, that doesn't actually need to be an AstModule: the Module base class is enough. This patch should cause no functional change, but the point is that it's now possible to call genRTLIL with a module that isn't an AstModule as "current_module". This will be needed for 'bind' support.
* verilog: Use proc memory writes in the frontend.Marcelina Kościelnicka2021-03-081-0/+2
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* frontend: Make helper functions for printing locations.Marcelina Kościelnicka2021-02-231-0/+6
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* Merge pull request #2594 from zachjs/func-arg-widthwhitequark2021-02-231-1/+7
|\ | | | | verilog: fix sizing of constant args for tasks/functions
| * verilog: fix sizing of constant args for tasks/functionsZachary Snow2021-02-211-1/+7
| | | | | | | | | | | | | | | | | | | | | | | | - Simplify synthetic localparams for normal calls to update their width - This step was inadvertently removed alongside `added_mod_children` - Support redeclaration of constant function arguments - `eval_const_function` never correctly handled this, but the issue was not exposed in the existing tests until the recent change to always attempt constant function evaluation when all-const args are used - Check asserts in const_arg_loop and const_func tests - Add coverage for width mismatch error cases
* | verilog: support recursive functions using ternary expressionsZachary Snow2021-02-121-0/+3
|/ | | | | | | This adds a mechanism for marking certain portions of elaboration as occurring within unevaluated ternary branches. To enable elaboration of the overall ternary, this also adds width detection for these unelaborated function calls.
* verilog: refactored constant function evaluationZachary Snow2021-02-041-4/+3
| | | | | | | | | | | Elaboration now attempts constant evaluation of any function call with only constant arguments, regardless of the context or contents of the function. This removes the concept of "recommended constant evaluation" which previously applied to functions with `for` loops or which were (sometimes erroneously) identified as recursive. Any function call in a constant context (e.g., `localparam`) or which contains a constant-only procedural construct (`while` or `repeat`) in its body will fail as before if constant evaluation does not succeed.
* verilog: significant block scoping improvementsZachary Snow2021-01-311-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This change set contains a number of bug fixes and improvements related to scoping and resolution in generate and procedural blocks. While many of the frontend changes are interdependent, it may be possible bring the techmap changes in under a separate PR. Declarations within unnamed generate blocks previously encountered issues because the data declarations were left un-prefixed, breaking proper scoping. The LRM outlines behavior for generating names for unnamed generate blocks. The original goal was to add this implicit labelling, but doing so exposed a number of issues downstream. Additional testing highlighted other closely related scope resolution issues, which have been fixed. This change also adds support for block item declarations within unnamed blocks in SystemVerilog mode. 1. Unlabled generate blocks are now implicitly named according to the LRM in `label_genblks`, which is invoked at the beginning of module elaboration 2. The Verilog parser no longer wraps explicitly named generate blocks in a synthetic unnamed generate block to avoid creating extra hierarchy levels where they should not exist 3. The techmap phase now allows special control identifiers to be used outside of the topmost scope, which is necessary because such wires and cells often appear in unlabeled generate blocks, which now prefix the declarations within 4. Some techlibs required modifications because they relied on the previous invalid scope resolution behavior 5. `expand_genblock` has been simplified, now only expanding the outermost scope, completely deferring the inspection and elaboration of nested scopes; names are now resolved by looking in the innermost scope and stepping outward 6. Loop variables now always become localparams during unrolling, allowing them to be resolved and shadowed like any other identifier 7. Identifiers in synthetic function call scopes are now prefixed and resolved in largely the same manner as other blocks before: `$func$\func_01$tests/simple/scopes.blk.v:60$5$\blk\x` after: `\func_01$func$tests/simple/scopes.v:60$5.blk.x` 8. Support identifiers referencing a local generate scope nested more than 1 level deep, i.e. `B.C.x` while within generate scope `A`, or using a prefix of a current or parent scope, i.e. `B.C.D.x` while in `A.B`, `A.B.C`, or `A.B.C.D` 9. Variables can now be declared within unnamed blocks in SystemVerilog mode Addresses the following issues: 656, 2423, 2493
* verilog: improved support for recursive functionsZachary Snow2020-12-311-0/+2
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* Added $high(), $low(), $left(), $right()Udi Finkelstein2020-09-151-0/+1
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* Fix generate scoping issuesZachary Snow2020-07-311-1/+1
| | | | | | | | | - expand_genblock defers prefixing of items within named sub-blocks - Allow partially-qualified references to local scopes - Handle shadowing within generate blocks - Resolve generate scope references within tasks and functions - Apply generate scoping to genvars - Resolves #2214, resolves #1456
* static cast: support changing size and signednessKazuki Sakamoto2020-06-191-0/+1
| | | | | | | | | Support SystemVerilog Static Cast - size - signedness - (type is not supposted yet) Fix #535
* Use C++11 final/override keywords.whitequark2020-06-181-5/+5
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* Add latch detection for use_case_method in part-select write, fixes #2040Claire Wolf2020-06-041-0/+1
| | | | Signed-off-by: Claire Wolf <claire@symbioticeda.com>
* Generalise structs and add support for packed unions.Peter Crozier2020-05-121-0/+1
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* Implement SV structs.Peter Crozier2020-05-081-2/+5
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* Add AST_SELFSZ and improve handling of bit slicesClaire Wolf2020-05-021-0/+1
| | | | Signed-off-by: Claire Wolf <claire@symbioticeda.com>
* Add "nowrshmsk" attribute, fix shift-and-mask bit slice write for signed ↵Claire Wolf2020-05-021-0/+2
| | | | | | offset, fixes #1990 Signed-off-by: Claire Wolf <claire@symbioticeda.com>
* Add LookaheadRewriter for proper bitselwrite supportClaire Wolf2020-04-161-0/+4
| | | | Signed-off-by: Claire Wolf <claire@symbioticeda.com>
* kernel: more pass by const ref, more speedupsEddie Hung2020-03-181-4/+4
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* Merge pull request #1718 from boqwxp/precise_locationsClaire Wolf2020-03-031-1/+8
|\ | | | | Closes #1717. Add more precise Verilog source location information to AST and RTLIL nodes.
| * Closes #1717. Add more precise Verilog source location information to AST ↵Alberto Gonzalez2020-02-231-1/+8
| | | | | | | | and RTLIL nodes.
* | ast: quiet down when deriving blackbox modulesEddie Hung2020-02-271-1/+1
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* Merge pull request #1642 from jjj11x/jjj11x/sv-enumClaire Wolf2020-02-201-0/+7
|\ | | | | Enum support
| * partial rebase of PeterCrozier's enum work onto current masterJeff Wang2020-01-161-0/+7
| | | | | | | | | | | | | | | | | | | | | | I tried to keep only the enum-related changes, and minimize the diff. (The original commit also had a lot of work done to get typedefs working, but yosys has diverged quite a bit since the 2018-03-09 commit, with a new typedef implementation.) I did not include the import related changes either. Original commit: "Initial implementation of enum, typedef, import. Still a WIP." https://github.com/PeterCrozier/yosys/commit/881833aa738e7404987646ea8076284e911fce3f
* | ast: Add support for $sformatf system functionDavid Shah2020-01-191-0/+1
|/ | | | Signed-off-by: David Shah <dave@ds0.me>
* Use "(id)" instead of "id" for types as temporary hackClifford Wolf2019-10-141-2/+5
|\ | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * sv: Switch parser to glr, prep for typedefDavid Shah2019-10-031-2/+5
| | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | module->derive() to be lazy and not touch ast if already derivedEddie Hung2019-09-301-1/+1
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* Fix handling of read_verilog config in AstModule::reprocess_module(), fixes ↵Clifford Wolf2019-09-201-0/+1
| | | | | | #1360 Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Add "read_verilog -pwires" feature, closes #1106Clifford Wolf2019-06-191-3/+3
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Fixes and cleanups in AST_TECALL handlingClifford Wolf2019-06-071-1/+0
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Merge branch 'pr_elab_sys_tasks' of https://github.com/udif/yosys into ↵Clifford Wolf2019-06-071-1/+3
|\ | | | | | | clifford/pr983
| * Initial implementation of elaboration system tasksUdi Finkelstein2019-05-031-1/+3
| | | | | | | | | | | | | | (IEEE1800-2017 section 20.11) This PR allows us to use $info/$warning/$error/$fatal **at elaboration time** within a generate block. This is very useful to stop a synthesis of a parametrized block when an illegal combination of parameters is chosen.
* | Merge branch 'master' into wandworStefan Biereigel2019-05-271-1/+3
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| * | Added support for unsized constants, fixes #1022Miodrag Milanovic2019-05-271-1/+3
| |/ | | | | | | Includes work from @sumit0190 and @AaronKel
* | remove leftovers from ast data structuresStefan Biereigel2019-05-271-1/+0
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* | fix indentation across filesStefan Biereigel2019-05-231-1/+1
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