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* Fix generate scoping issuesZachary Snow2020-07-311-1/+1
| | | | | | | | | - expand_genblock defers prefixing of items within named sub-blocks - Allow partially-qualified references to local scopes - Handle shadowing within generate blocks - Resolve generate scope references within tasks and functions - Apply generate scoping to genvars - Resolves #2214, resolves #1456
* static cast: support changing size and signednessKazuki Sakamoto2020-06-191-0/+1
| | | | | | | | | Support SystemVerilog Static Cast - size - signedness - (type is not supposted yet) Fix #535
* Use C++11 final/override keywords.whitequark2020-06-181-5/+5
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* Add latch detection for use_case_method in part-select write, fixes #2040Claire Wolf2020-06-041-0/+1
| | | | Signed-off-by: Claire Wolf <claire@symbioticeda.com>
* Generalise structs and add support for packed unions.Peter Crozier2020-05-121-0/+1
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* Implement SV structs.Peter Crozier2020-05-081-2/+5
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* Add AST_SELFSZ and improve handling of bit slicesClaire Wolf2020-05-021-0/+1
| | | | Signed-off-by: Claire Wolf <claire@symbioticeda.com>
* Add "nowrshmsk" attribute, fix shift-and-mask bit slice write for signed ↵Claire Wolf2020-05-021-0/+2
| | | | | | offset, fixes #1990 Signed-off-by: Claire Wolf <claire@symbioticeda.com>
* Add LookaheadRewriter for proper bitselwrite supportClaire Wolf2020-04-161-0/+4
| | | | Signed-off-by: Claire Wolf <claire@symbioticeda.com>
* kernel: more pass by const ref, more speedupsEddie Hung2020-03-181-4/+4
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* Merge pull request #1718 from boqwxp/precise_locationsClaire Wolf2020-03-031-1/+8
|\ | | | | Closes #1717. Add more precise Verilog source location information to AST and RTLIL nodes.
| * Closes #1717. Add more precise Verilog source location information to AST ↵Alberto Gonzalez2020-02-231-1/+8
| | | | | | | | and RTLIL nodes.
* | ast: quiet down when deriving blackbox modulesEddie Hung2020-02-271-1/+1
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* Merge pull request #1642 from jjj11x/jjj11x/sv-enumClaire Wolf2020-02-201-0/+7
|\ | | | | Enum support
| * partial rebase of PeterCrozier's enum work onto current masterJeff Wang2020-01-161-0/+7
| | | | | | | | | | | | | | | | | | | | | | I tried to keep only the enum-related changes, and minimize the diff. (The original commit also had a lot of work done to get typedefs working, but yosys has diverged quite a bit since the 2018-03-09 commit, with a new typedef implementation.) I did not include the import related changes either. Original commit: "Initial implementation of enum, typedef, import. Still a WIP." https://github.com/PeterCrozier/yosys/commit/881833aa738e7404987646ea8076284e911fce3f
* | ast: Add support for $sformatf system functionDavid Shah2020-01-191-0/+1
|/ | | | Signed-off-by: David Shah <dave@ds0.me>
* Use "(id)" instead of "id" for types as temporary hackClifford Wolf2019-10-141-2/+5
|\ | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * sv: Switch parser to glr, prep for typedefDavid Shah2019-10-031-2/+5
| | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | module->derive() to be lazy and not touch ast if already derivedEddie Hung2019-09-301-1/+1
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* Fix handling of read_verilog config in AstModule::reprocess_module(), fixes ↵Clifford Wolf2019-09-201-0/+1
| | | | | | #1360 Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Add "read_verilog -pwires" feature, closes #1106Clifford Wolf2019-06-191-3/+3
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Fixes and cleanups in AST_TECALL handlingClifford Wolf2019-06-071-1/+0
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Merge branch 'pr_elab_sys_tasks' of https://github.com/udif/yosys into ↵Clifford Wolf2019-06-071-1/+3
|\ | | | | | | clifford/pr983
| * Initial implementation of elaboration system tasksUdi Finkelstein2019-05-031-1/+3
| | | | | | | | | | | | | | (IEEE1800-2017 section 20.11) This PR allows us to use $info/$warning/$error/$fatal **at elaboration time** within a generate block. This is very useful to stop a synthesis of a parametrized block when an illegal combination of parameters is chosen.
* | Merge branch 'master' into wandworStefan Biereigel2019-05-271-1/+3
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| * | Added support for unsized constants, fixes #1022Miodrag Milanovic2019-05-271-1/+3
| |/ | | | | | | Includes work from @sumit0190 and @AaronKel
* | remove leftovers from ast data structuresStefan Biereigel2019-05-271-1/+0
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* | fix indentation across filesStefan Biereigel2019-05-231-1/+1
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* | implementation for assignments workingStefan Biereigel2019-05-231-0/+1
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* | make lexer/parser aware of wand/wor net typesStefan Biereigel2019-05-231-1/+1
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* New behavior for front-end handling of whiteboxesClifford Wolf2019-04-201-2/+2
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Add "whitebox" attribute, add "read_verilog -wb"Clifford Wolf2019-04-181-2/+2
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Improve read_verilog debug output capabilitiesClifford Wolf2019-03-211-1/+1
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Only run derive on blackbox modules when ports have dynamic sizeClifford Wolf2019-03-021-0/+1
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Use mem2reg on memories that only have constant-index write portsClifford Wolf2019-03-011-0/+2
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Refactor code to avoid code duplication + added commentsRuben Undheim2018-10-201-0/+5
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* Support for 'modports' for System Verilog interfacesRuben Undheim2018-10-121-1/+3
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* Synthesis support for SystemVerilog interfacesRuben Undheim2018-10-121-0/+6
| | | | This time doing the changes mostly in AST before RTLIL generation
* Added -no_dump_ptr flag for AST dump options in 'read_verilog'Udi Finkelstein2018-08-231-2/+2
| | | | | | This option disables the memory pointer display. This is useful when diff'ing different dumps because otherwise the node pointers makes every diff line different when the AST content is the same.
* Merge pull request #591 from hzeller/virtual-overrideClifford Wolf2018-08-151-4/+4
|\ | | | | Consistent use of 'override' for virtual methods in derived classes.
| * Consistent use of 'override' for virtual methods in derived classes.Henner Zeller2018-07-201-4/+4
| | | | | | | | | | | | | | | | | | o Not all derived methods were marked 'override', but it is a great feature of C++11 that we should make use of. o While at it: touched header files got a -*- c++ -*- for emacs to provide support for that language. o use YS_OVERRIDE for all override keywords (though we should probably use the plain keyword going forward now that C++11 is established)
* | Merge pull request #513 from udif/pr_reg_wire_errorClifford Wolf2018-08-151-1/+1
|\ \ | |/ |/| Add error checking for reg/wire/logic misuse - PR now passes 'make test' (plus a new test)
| * Modified errors into warningsUdi Finkelstein2018-06-051-1/+1
| | | | | | | | No longer false warnings for memories and assertions
| * This PR should be the base for discussion, do not merge it yet!Udi Finkelstein2018-03-111-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | It correctly detects reg/wire mix and incorrect use on blocking,nonblocking assignments within blocks and assign statements. What it DOES'T do: Detect registers connected to output ports of instances. Where it FAILS: memorty nonblocking assignments causes spurious (I assume??) errors on yosys-generated "_ADDR", "_DATA", "EN" signals. You can test it with tests/simple/reg_wire_error.v (look inside for the comments to enable/disable specific lines)
* | Replace -ignore_redef with -[no]overwriteClifford Wolf2018-05-031-1/+1
|/ | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Bugfix in hierarchy handling of blackbox module portsClifford Wolf2018-01-051-1/+1
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Turned a few member functions into const, esp. dumpAst(), dumpVlog().Udi Finkelstein2017-09-301-7/+7
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* Add $live and $fair cell types, add support for s_eventually keywordClifford Wolf2017-02-251-0/+2
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* Add $cover cell type and SVA cover() supportClifford Wolf2017-02-041-0/+1
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* Avoid creation of bogus initial blocks for assert/assume in always @*Clifford Wolf2016-09-061-0/+1
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