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* Merge pull request #1718 from boqwxp/precise_locationsClaire Wolf2020-03-031-102/+101
|\ | | | | Closes #1717. Add more precise Verilog source location information to AST and RTLIL nodes.
| * Closes #1717. Add more precise Verilog source location information to AST ↵Alberto Gonzalez2020-02-231-102/+101
| | | | | | | | and RTLIL nodes.
* | ast: fixes #1710; do not generate RTLIL for unreachable ternaryEddie Hung2020-02-271-9/+22
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* Merge pull request #1703 from YosysHQ/eddie/specify_improveEddie Hung2020-02-211-7/+11
|\ | | | | Improve specify parser
| * verilog: fix $specify3 checkEddie Hung2020-02-131-7/+11
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* | partial rebase of PeterCrozier's enum work onto current masterJeff Wang2020-01-161-2/+6
|/ | | | | | | | | | | I tried to keep only the enum-related changes, and minimize the diff. (The original commit also had a lot of work done to get typedefs working, but yosys has diverged quite a bit since the 2018-03-09 commit, with a new typedef implementation.) I did not include the import related changes either. Original commit: "Initial implementation of enum, typedef, import. Still a WIP." https://github.com/PeterCrozier/yosys/commit/881833aa738e7404987646ea8076284e911fce3f
* sv: Switch parser to glr, prep for typedefDavid Shah2019-10-031-0/+1
| | | | Signed-off-by: David Shah <dave@ds0.me>
* substr() -> compare()Eddie Hung2019-08-071-1/+1
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* genrtlil: emit \src attribute on CaseRule.whitequark2019-07-081-0/+1
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* Add "read_verilog -pwires" feature, closes #1106Clifford Wolf2019-06-191-1/+20
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Fixes and cleanups in AST_TECALL handlingClifford Wolf2019-06-071-1/+31
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Merge branch 'pr_elab_sys_tasks' of https://github.com/udif/yosys into ↵Clifford Wolf2019-06-071-0/+1
|\ | | | | | | clifford/pr983
| * Initial implementation of elaboration system tasksUdi Finkelstein2019-05-031-0/+1
| | | | | | | | | | | | | | (IEEE1800-2017 section 20.11) This PR allows us to use $info/$warning/$error/$fatal **at elaboration time** within a generate block. This is very useful to stop a synthesis of a parametrized block when an illegal combination of parameters is chosen.
* | Merge branch 'master' into wandworStefan Biereigel2019-05-271-3/+9
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| * \ Merge pull request #1044 from mmicko/invalid_width_rangeClifford Wolf2019-05-271-1/+2
| |\ \ | | | | | | | | Give error instead of asserting for invalid range, fixes #947
| | * | Give error instead of asserting for invalid range, fixes #947Miodrag Milanovic2019-05-271-1/+2
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| * | | Added support for unsized constants, fixes #1022Miodrag Milanovic2019-05-271-2/+7
| |/ / | | | | | | | | | Includes work from @sumit0190 and @AaronKel
* | | move wand/wor resolution into hierarchy passStefan Biereigel2019-05-271-97/+14
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* | | fix assignment of non-wiresStefan Biereigel2019-05-231-16/+19
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* | | fix indentation across filesStefan Biereigel2019-05-231-58/+76
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* | | implementation for assignments workingStefan Biereigel2019-05-231-14/+79
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* | Improve write_verilog specify supportClifford Wolf2019-05-041-0/+3
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | Merge remote-tracking branch 'origin/master' into clifford/specifyEddie Hung2019-05-031-0/+2
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| * | Fix width detection of memory access with bit slice, fixes #974Clifford Wolf2019-05-011-0/+2
| |/ | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | Add $specrule cells for $setup/$hold/$skew specify rulesClifford Wolf2019-04-231-0/+6
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | Checking and fixing specify cells in genRTLILClifford Wolf2019-04-231-1/+15
|/ | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Improve handling of "full_case" attributesClifford Wolf2019-03-141-0/+9
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Add support for SVA labels in read_verilogClifford Wolf2019-03-071-3/+9
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Fix error for wire decl in always block, fixes #763Clifford Wolf2019-03-021-1/+5
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Fixes related to handling of autowires and upto-ranges, fixes #814Clifford Wolf2019-02-211-2/+2
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Fix segfault in printing of some internal error messagesClifford Wolf2019-02-211-2/+2
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Fix sign handling of real constantsClifford Wolf2019-02-131-5/+4
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Various indenting fixes in AST front-end (mostly space vs tab issues)Clifford Wolf2018-11-041-55/+33
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Improve read_verilog range out of bounds warningClifford Wolf2018-10-201-6/+6
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Refactor code to avoid code duplication + added commentsRuben Undheim2018-10-201-21/+4
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* Documentation improvements etc.Ruben Undheim2018-10-131-5/+7
| | | | | | | | | - Mention new feature in the SystemVerilog section in the README file - Commented changes much better - Rename a few signals to make it clearer - Prevent warning for unused signals in an easier way - Add myself as copyright holder to 2 files - Fix one potential memory leak (delete 'wire' if not in modport)
* Support for 'modports' for System Verilog interfacesRuben Undheim2018-10-121-0/+29
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* Synthesis support for SystemVerilog interfacesRuben Undheim2018-10-121-2/+46
| | | | This time doing the changes mostly in AST before RTLIL generation
* Fix for issue 594.Tom Verbeure2018-10-021-1/+2
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* Convert more log_error() to log_file_error() where possible.Henner Zeller2018-07-201-71/+69
| | | | | Mostly statements that span over multiple lines and haven't been caught with the previous conversion.
* Use log_file_warning(), log_file_error() functions.Henner Zeller2018-07-201-16/+16
| | | | Wherever we can report a source-level location.
* Provide source-location logging.Henner Zeller2018-07-191-3/+2
| | | | | | | | o Provide log_file_warning() and log_file_error() that prefix the log message with <filename>:<lineno>: to be easily picked up by IDEs that need to step through errors. o Simplify some duplicate logging code in kernel/log.cc o Use the new log functions in genrtlil.
* Fix handling of signed memoriesClifford Wolf2018-06-281-0/+3
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Add (* gclk *) attribute supportClifford Wolf2018-06-011-0/+9
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Add $allconst and $allseq cell typesClifford Wolf2018-02-231-2/+2
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Fix error handling for nested always/initialClifford Wolf2017-12-021-0/+2
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* Fix generation of vlogtb output in yosys-smtbmc for "rand reg" and "rand ↵Clifford Wolf2017-06-071-0/+7
| | | | const reg"
* Add $live and $fair cell types, add support for s_eventually keywordClifford Wolf2017-02-251-1/+6
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* Add $cover cell type and SVA cover() supportClifford Wolf2017-02-041-0/+2
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* Some fixes in handling of signed arraysClifford Wolf2016-11-011-0/+1
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