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* Creating $meminit cells in verilog front-endClifford Wolf2015-02-141-6/+9
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* Ignore explicit assignments to constants in HDL codeClifford Wolf2015-02-081-0/+14
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* Fixed a bug with autowire bit sizeClifford Wolf2015-02-081-9/+3
| | | | (removed leftover from when we tried to auto-size the wires)
* Fixed memory->start_offset handlingClifford Wolf2015-01-011-6/+7
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* Changed more code to dict<> and pool<>Clifford Wolf2014-12-281-3/+3
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* Renamed extend() to extend_xx(), changed most users to extend_u0()Clifford Wolf2014-12-241-1/+1
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* Added log_warning() APIClifford Wolf2014-11-091-6/+6
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* Renamed SIZE() to GetSize() because of name collision on Win32Clifford Wolf2014-10-101-8/+8
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* Fixed assignment of out-of bounds array elementClifford Wolf2014-09-061-2/+26
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* Removed $bu0 cell typeClifford Wolf2014-09-041-5/+5
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* Added Verilog/AST support for DPI functions (dpi_call() still unimplemented)Clifford Wolf2014-08-211-0/+1
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* Improved AST ProcessGenerator performanceClifford Wolf2014-08-171-3/+3
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* Use stackmap<> in AST ProcessGeneratorClifford Wolf2014-08-171-21/+19
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* AST ProcessGenerator: replaced subst_*_{from,to} with subst_*_mapClifford Wolf2014-08-161-41/+26
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* Added RTLIL::SigSpec::to_sigbit_map()Clifford Wolf2014-08-141-11/+3
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* Changed the AST genWidthRTLIL subst interface to use a std::mapClifford Wolf2014-08-141-17/+27
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* More cleanups related to RTLIL::IdString usageClifford Wolf2014-08-021-6/+6
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* Renamed port access function on RTLIL::Cell, added param access functionsClifford Wolf2014-07-311-22/+22
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* Moved some stuff to kernel/yosys.{h,cc}, using Yosys:: namespaceClifford Wolf2014-07-311-10/+14
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* Added $shift and $shiftx cell types (needed for correct part select behavior)Clifford Wolf2014-07-291-5/+11
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* Removed left over debug codeClifford Wolf2014-07-281-1/+0
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* Fixed part selects of parametersClifford Wolf2014-07-281-5/+10
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* Set results of out-of-bounds static bit/part select to undefClifford Wolf2014-07-281-5/+31
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* Fixed RTLIL code generator for part select of parameterClifford Wolf2014-07-281-2/+2
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* Fixed width detection for part selectsClifford Wolf2014-07-281-2/+2
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* Added support for "upto" wires to Verilog front- and back-endClifford Wolf2014-07-281-11/+8
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* Added wire->upto flag for signals such as "wire [0:7] x;"Clifford Wolf2014-07-281-0/+3
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* Using log_assert() instead of assert()Clifford Wolf2014-07-281-12/+11
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* Fixed signdness detection of expressions with bit- and part-selectsClifford Wolf2014-07-281-0/+1
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* Refactoring: Renamed RTLIL::Module::wires to wires_Clifford Wolf2014-07-271-5/+5
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* Changed a lot of code to the new RTLIL::Wire constructorsClifford Wolf2014-07-261-13/+9
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* Manual fixes for new cell connections APIClifford Wolf2014-07-261-2/+2
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* Changed users of cell->connections_ to the new API (sed command)Clifford Wolf2014-07-261-24/+24
| | | | | | | | | git grep -l 'connections_' | xargs sed -i -r -e ' s/(->|\.)connections_\["([^"]*)"\] = (.*);/\1set("\2", \3);/g; s/(->|\.)connections_\["([^"]*)"\]/\1get("\2")/g; s/(->|\.)connections_.at\("([^"]*)"\)/\1get("\2")/g; s/(->|\.)connections_.push_back/\1connect/g; s/(->|\.)connections_/\1connections()/g;'
* Renamed RTLIL::{Module,Cell}::connections to connections_Clifford Wolf2014-07-261-24/+24
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* Use only module->addCell() and module->remove() to create and delete cellsClifford Wolf2014-07-251-54/+19
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* Replaced more old SigChunk programming patternsClifford Wolf2014-07-241-7/+7
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* Removed RTLIL::SigSpec::optimize()Clifford Wolf2014-07-231-11/+0
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* SigSpec refactoring: More cleanups of old SigSpec use patternClifford Wolf2014-07-221-3/+6
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* SigSpec refactoring: change RTLIL::SigSpec::chunks() to be read-only, ↵Clifford Wolf2014-07-221-1/+1
| | | | created interim RTLIL::SigSpec::chunks_rw()
* SigSpec refactoring: change RTLIL::SigSpec::size() to be read-onlyClifford Wolf2014-07-221-55/+11
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* SigSpec refactoring: using the accessor functions everywhereClifford Wolf2014-07-221-60/+60
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* SigSpec refactoring: renamed chunks and width to __chunks and __widthClifford Wolf2014-07-221-60/+60
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* changes in verilog frontend for new $mem/$memwr WR_EN interfaceClifford Wolf2014-07-161-3/+0
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* More found_real-related fixes to AstNode::detectSignWidthWorkerClifford Wolf2014-06-241-6/+6
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* fixed signdness detection for expressions with realsClifford Wolf2014-06-211-2/+8
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* Added found_real feature to AstNode::detectSignWidthClifford Wolf2014-06-161-4/+9
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* improved (fixed) conversion of real values to bit vectorsClifford Wolf2014-06-141-4/+4
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* Added real->int convertion in ast genrtlilClifford Wolf2014-06-141-0/+12
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* further improved const function supportClifford Wolf2014-06-071-5/+5
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* improved const function supportClifford Wolf2014-06-061-1/+1
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