iCE40/yosys - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
*	Added defparam support to Verilog/AST frontend	Clifford Wolf	2013-07-04	1	-2/+18
*	Fixes and improvements in AST const folding	Clifford Wolf	2013-06-10	1	-0/+10
*	Enabled AST/Verilog front-end optimizations per default	Clifford Wolf	2013-06-10	1	-1/+1
*	Merge branch 'bugfix'	Clifford Wolf	2013-05-16	1	-2/+0
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\| *	Fixed synthesis of functions in latched blocks	Clifford Wolf	2013-05-16	1	-2/+0
* \|	Added AST_INITIAL (before verilog "initial" was mapped to AST_ALWAYS)	Clifford Wolf	2013-03-31	1	-1/+1
* \|	Improvements and bugfixes for generate blocks with local signals	Clifford Wolf	2013-03-26	1	-3/+1
* \|	Fixed handling of unconditional generate blocks	Clifford Wolf	2013-03-26	1	-1/+18
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*	Added nosync attribute and some async reset related fixes	Clifford Wolf	2013-03-25	1	-30/+10
*	Added mem2reg option to verilog frontend	Clifford Wolf	2013-03-24	1	-4/+7
*	Another fix in mem2reg ast simplify logic	Clifford Wolf	2013-03-24	1	-1/+3
*	Improved mem2reg handling in ast simplifier	Clifford Wolf	2013-03-24	1	-4/+34
*	Tiny fixes to verilog parser	Clifford Wolf	2013-03-23	1	-0/+3
*	Moved stand-alone libs to libs/ directory and added libs/subcircuit	Clifford Wolf	2013-02-27	1	-1/+1
*	Added support for verilog genblock[index].member syntax	Clifford Wolf	2013-02-26	1	-1/+15
*	initial import	Clifford Wolf	2013-01-05	1	-0/+1081