iCE40/yosys - [no description]

	Commit message (Collapse)	Author	Age	Files	Lines
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*	Fixed algorithmic complexity of AST simplification of long expressions	Clifford Wolf	2014-01-20	1	-6/+9
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*	Added $assert cell	Clifford Wolf	2014-01-19	1	-0/+60
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*	Fixed typo in frontends/ast/simplify.cc	Clifford Wolf	2014-01-12	1	-1/+1
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*	Fixed a stupid access after delete bug	Clifford Wolf	2013-12-29	1	-1/+2
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*	Added proper === and !== support in constant expressions	Clifford Wolf	2013-12-27	1	-6/+10
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*	Keep strings as strings in const ternary and concat	Clifford Wolf	2013-12-05	1	-3/+10
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*	Added const folding support for $signed and $unsigned	Clifford Wolf	2013-12-05	1	-0/+7
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*	Fixed generate-for (and disabled double warning for auto-wire)	Clifford Wolf	2013-12-04	1	-1/+5
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*	Added support for $clog2 system function	Clifford Wolf	2013-12-04	1	-4/+20
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*	Various improvements in support for generate statements	Clifford Wolf	2013-12-04	1	-2/+78
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*	Added support for local regs in named blocks	Clifford Wolf	2013-12-04	1	-0/+21
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*	Early wire/reg/parameter width calculation in ast/simplify	Clifford Wolf	2013-11-24	1	-0/+5
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*	Fixed async proc detection in mem2reg	Clifford Wolf	2013-11-21	1	-5/+9
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*	Major improvements in mem2reg and added "init" sync rules	Clifford Wolf	2013-11-21	1	-82/+198
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*	Another name resolution bugfix for generate blocks	Clifford Wolf	2013-11-20	1	-4/+13
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*	Do not allow memory bit select on the left side of an assignment	Clifford Wolf	2013-11-20	1	-1/+1
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*	Fixed name resolution of local tasks and functions in generate block	Clifford Wolf	2013-11-20	1	-2/+16
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*	Implemented part/bit select on memory read	Clifford Wolf	2013-11-20	1	-2/+51
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*	Fixed two bugs in mem2reg functionality in AST frontend	Clifford Wolf	2013-11-18	1	-4/+8
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*	Fixed mem2reg for reg usage outside always block	Clifford Wolf	2013-11-18	1	-1/+1
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*	Fixed handling of different signedness in power operands	Clifford Wolf	2013-11-08	1	-1/+1
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*	Implemented const folding of ternary op with undef select	Clifford Wolf	2013-11-08	1	-0/+8
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*	Fixed handling of power operator	Clifford Wolf	2013-11-07	1	-2/+2
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*	Fixed more extend vs. extend_u0 issues	Clifford Wolf	2013-11-07	1	-1/+1
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*	Disabled const folding of ternary op when select is undef	Clifford Wolf	2013-11-07	1	-2/+14
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*	Fixed sign handling in constants	Clifford Wolf	2013-11-07	1	-0/+1
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*	Fixed const folding in corner cases with parameters	Clifford Wolf	2013-11-07	1	-10/+20
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*	Fixed at_zero evaluation of dynamic ranges	Clifford Wolf	2013-11-07	1	-7/+2
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*	Various fixes for correct parameter support	Clifford Wolf	2013-11-07	1	-0/+25
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*	Another fix for early width and sign detection in ast simplifier	Clifford Wolf	2013-11-04	1	-2/+3
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*	Fixed const folding of ternary operator	Clifford Wolf	2013-11-04	1	-4/+5
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*	Use proper bit width ans sign extension for const folding	Clifford Wolf	2013-11-04	1	-17/+18
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*	Fixes for early width and sign detection in ast simplifier	Clifford Wolf	2013-11-04	1	-1/+2
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*	further improved early width and sign detection in ast simplifier	Clifford Wolf	2013-11-04	1	-9/+112
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*	Behavior should be identical now to rev. 0b4a64ac6adbd6 (next: testing ↵	Clifford Wolf	2013-11-02	1	-2/+4
\| \| \| \|	before constfold fixes)
*	Various ast changes for early expression width detection (prep for constfold ↵	Clifford Wolf	2013-11-02	1	-13/+38
\| \| \| \|	fixes)
*	Fixed handling of boolean attributes (frontends)	Clifford Wolf	2013-10-24	1	-8/+8
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*	Added support for notif0/notif1 primitives	Johann Glaser	2013-08-20	1	-3/+7
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*	Added support for bufif0/bufif1 primitives	Clifford Wolf	2013-08-19	1	-32/+58
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*	Improved ast dumping (ast/verilog frontend)	Clifford Wolf	2013-08-19	1	-1/+1
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*	Added defparam support to Verilog/AST frontend	Clifford Wolf	2013-07-04	1	-2/+18
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*	Fixes and improvements in AST const folding	Clifford Wolf	2013-06-10	1	-0/+10
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*	Enabled AST/Verilog front-end optimizations per default	Clifford Wolf	2013-06-10	1	-1/+1
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*	Merge branch 'bugfix'	Clifford Wolf	2013-05-16	1	-2/+0
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\| *	Fixed synthesis of functions in latched blocks	Clifford Wolf	2013-05-16	1	-2/+0
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* \|	Added AST_INITIAL (before verilog "initial" was mapped to AST_ALWAYS)	Clifford Wolf	2013-03-31	1	-1/+1
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* \|	Improvements and bugfixes for generate blocks with local signals	Clifford Wolf	2013-03-26	1	-3/+1
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* \|	Fixed handling of unconditional generate blocks	Clifford Wolf	2013-03-26	1	-1/+18
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*	Added nosync attribute and some async reset related fixes	Clifford Wolf	2013-03-25	1	-30/+10
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*	Added mem2reg option to verilog frontend	Clifford Wolf	2013-03-24	1	-4/+7
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