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* Fixed a bug in the new feature of $readmem[hb] when an empty string is providedRodrigo Alejandro Melo2020-02-011-1/+1
| | | | Signed-off-by: Rodrigo Alejandro Melo <rodrigomelo9@gmail.com>
* Modified the new search for files of $readmem[hb] to be backward compatibleRodrigo Alejandro Melo2020-01-311-3/+7
| | | | Signed-off-by: Rodrigo Alejandro Melo <rodrigomelo9@gmail.com>
* $readmem[hb] file inclusion is now relative to the Verilog fileRodrigo Alejandro Melo2020-01-311-1/+2
| | | | Signed-off-by: Rodrigo Alejandro Melo <rodrigomelo9@gmail.com>
* Stray log_dumpEddie Hung2019-12-111-1/+0
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* Preserve size of $genval$-s in for loopsEddie Hung2019-12-111-0/+17
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* frontends/ast: code styleDavid Shah2019-10-031-2/+1
| | | | Signed-off-by: David Shah <dave@ds0.me>
* sv: Fix typedefs in blocksDavid Shah2019-10-031-2/+2
| | | | Signed-off-by: David Shah <dave@ds0.me>
* sv: Add support for memories of a typedefDavid Shah2019-10-031-6/+20
| | | | Signed-off-by: David Shah <dave@ds0.me>
* sv: Add support for memory typedefsDavid Shah2019-10-031-2/+15
| | | | Signed-off-by: David Shah <dave@ds0.me>
* sv: Fix typedefs in packagesDavid Shah2019-10-031-4/+10
| | | | Signed-off-by: David Shah <dave@ds0.me>
* sv: Fix typedef parametersDavid Shah2019-10-031-2/+31
| | | | Signed-off-by: David Shah <dave@ds0.me>
* sv: Switch parser to glr, prep for typedefDavid Shah2019-10-031-5/+46
| | | | Signed-off-by: David Shah <dave@ds0.me>
* Fix handling of range selects on loop variables, fixes #1372Clifford Wolf2019-09-161-2/+9
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Properly construct $live and $fair cells from "if (...) assume/assert ↵Clifford Wolf2019-09-021-7/+18
| | | | | | | | (s_eventually ...)" Fixes https://github.com/YosysHQ/SymbiYosys/issues/59 Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Do not propagate mem2reg attribute through to resultEddie Hung2019-08-221-1/+2
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* mem2reg to preserve user attributes and srcEddie Hung2019-08-211-0/+4
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* substr() -> compare()Eddie Hung2019-08-071-3/+3
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* Merge remote-tracking branch 'origin/master' into eddie/cleanupEddie Hung2019-08-071-15/+2
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| * Fix handling of functions/tasks without top-level begin-end block, fixes #1231Clifford Wolf2019-08-061-15/+2
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | IdString::str().substr() -> IdString::substr()Eddie Hung2019-08-061-1/+1
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* Merge branch 'master' of github.com:YosysHQ/yosys into clifford/fix968Clifford Wolf2019-05-061-0/+1
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| * Add splitcmplxassign test case and silence splitcmplxassign warningClifford Wolf2019-05-011-0/+1
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | Re-enable "final loop assignment" featureClifford Wolf2019-05-011-2/+0
|/ | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Disabled "final loop assignment" featureClifford Wolf2019-04-301-0/+2
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Add final loop variable assignment when unrolling for-loops, fixes #968Clifford Wolf2019-04-301-0/+7
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Determine correct signedness and expression width in for loop unrolling, ↵Clifford Wolf2019-04-221-3/+18
| | | | | | fixes #370 Signed-off-by: Clifford Wolf <clifford@clifford.at>
* support repeat loops with constant repeat counts outside of constant functionsZachary Snow2019-04-091-1/+20
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* Fix mem2reg handling of memories with upto data ports, fixes #888Clifford Wolf2019-03-211-1/+10
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* fix local name resolution in prefix constructsZachary Snow2019-03-181-1/+5
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* Improve handling of memories used in mem index expressions on LHS of an ↵Clifford Wolf2019-03-121-5/+16
| | | | | | assignment Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Remove outdated "blocking assignment to memory" warningClifford Wolf2019-03-121-10/+0
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Only set MEM2REG_FL_CONST_LHS/MEM2REG_FL_VAR_LHS for non-init writes, fixes #867Clifford Wolf2019-03-121-6/+8
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Merge pull request #858 from YosysHQ/clifford/svalabelsClifford Wolf2019-03-091-0/+1
|\ | | | | Add support for using SVA labels in yosys-smtbmc console output
| * Add support for SVA labels in read_verilogClifford Wolf2019-03-071-0/+1
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | Fix handling of task output ports in clocked always blocks, fixes #857Clifford Wolf2019-03-071-15/+18
|/ | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Only run derive on blackbox modules when ports have dynamic sizeClifford Wolf2019-03-021-0/+19
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Fix $global_clock handling vs autowireClifford Wolf2019-03-021-1/+1
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Fix $readmem[hb] for mem2reg memories, fixes #785Clifford Wolf2019-03-021-0/+35
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Use mem2reg on memories that only have constant-index write portsClifford Wolf2019-03-011-0/+11
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Fix handling of defparam for when default_nettype is noneClifford Wolf2019-02-241-0/+4
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Fixes related to handling of autowires and upto-ranges, fixes #814Clifford Wolf2019-02-211-7/+10
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Fix handling of expression width in $past, fixes #810Clifford Wolf2019-02-211-1/+1
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Fix segfault in AST simplifyClifford Wolf2018-12-181-0/+5
| | | | | | (as proposed by Dan Gisselquist) Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Make return value of $clog2 signedSylvain Munaut2018-11-241-1/+1
| | | | | | | | As per Verilog 2005 - 17.11.1. Fixes #708 Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
* Various indenting fixes in AST front-end (mostly space vs tab issues)Clifford Wolf2018-11-041-38/+33
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Make and dependent upon LSB onlyZipCPU2018-11-031-2/+8
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* Do not generate "reg assigned in a continuous assignment" warnings for "rand ↵Clifford Wolf2018-11-011-2/+15
| | | | | | reg" Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Merge pull request #659 from rubund/sv_interfacesClifford Wolf2018-10-181-1/+1
|\ | | | | Support for SystemVerilog interfaces and modports
| * Synthesis support for SystemVerilog interfacesRuben Undheim2018-10-121-1/+1
| | | | | | | | This time doing the changes mostly in AST before RTLIL generation
* | Merge pull request #638 from udif/pr_reg_wire_errorClifford Wolf2018-10-171-0/+12
|\ \ | |/ |/| Fix issue #630
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