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* Fixed some visual studio warningsClifford Wolf2016-02-133-4/+4
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* genrtlil: avoid converting SigSpec to set<SigBit> when going through ↵Rick Altherr2016-01-311-3/+3
| | | | removeSignalFromCaseTree()
* Fixed handling of re-declarations of wires in tasks and functionsClifford Wolf2015-11-231-7/+26
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* More bugfixes in handling of parameters in tasks and functionsClifford Wolf2015-11-121-1/+11
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* Fixed handling of parameters and localparams in functionsClifford Wolf2015-11-112-3/+8
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* Import more std:: stuff into Yosys namespaceClifford Wolf2015-10-252-32/+32
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* Fixed complexity of assigning to vectors in constant functionsClifford Wolf2015-10-011-0/+3
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* Fixed detection of unconditional $readmem[hb]Clifford Wolf2015-09-301-4/+11
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* Bugfixes in $readmem[hb]Clifford Wolf2015-09-251-4/+7
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* Fixed segfault in AstNode::asRealClifford Wolf2015-09-251-1/+1
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* Added read-enable to memory modelClifford Wolf2015-09-251-0/+1
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* Fixed AstNode::mkconst_bits() segfault on zero-sized constantClifford Wolf2015-09-241-1/+1
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* Bugfix in handling of multi-dimensional memoriesClifford Wolf2015-09-231-2/+2
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* Warning for $display/$write outside initial blockClifford Wolf2015-09-231-7/+8
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* Fixed multi-level prefix resolvingClifford Wolf2015-09-221-0/+2
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* Improvements to $display system taskAndrew Zonenberg2015-09-191-9/+22
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* Added AST_INITIAL checks for $finish and $displayClifford Wolf2015-09-181-2/+9
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* Initial implementation of $display()Andrew Zonenberg2015-09-181-1/+84
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* Initial implementation of $finish()Andrew Zonenberg2015-09-181-2/+8
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* Fixed handling of memory read without addressClifford Wolf2015-08-221-1/+1
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* Another block of spelling fixesLarry Doolittle2015-08-141-4/+4
| | | | Smaller this time
* Keep gcc from complaining about uninitialized variablesLarry Doolittle2015-08-141-2/+2
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* Spell check (by Larry Doolittle)Clifford Wolf2015-08-143-14/+14
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* Added WORDS parameter to $meminitClifford Wolf2015-07-313-7/+67
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* Fixed nested mem2regClifford Wolf2015-07-292-4/+11
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* Fixed trailing whitespacesClifford Wolf2015-07-025-12/+12
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* Fixed handling of parameters with reversed rangeClifford Wolf2015-06-081-1/+1
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* Fixed signedness of genvar expressionsClifford Wolf2015-05-291-2/+2
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* Const-fold parameter defs on-demand in AstNode::detectSignWidthWorker()Clifford Wolf2015-03-011-2/+4
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* Added non-std verilog assume() statementClifford Wolf2015-02-264-8/+12
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* Added deep recursion warning to AST simplifyClifford Wolf2015-02-201-1/+7
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* Parser support for complex delay expressionsClifford Wolf2015-02-201-1/+1
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* Convert floating point cell parameters to stringsClifford Wolf2015-02-181-9/+12
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* Various fixes for memories with offsetsClifford Wolf2015-02-142-6/+5
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* Added "read_verilog -nomeminit" and "nomeminit" attributeClifford Wolf2015-02-143-6/+14
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* Creating $meminit cells in verilog front-endClifford Wolf2015-02-144-33/+57
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* Added AstNode::simplify() recursion counterClifford Wolf2015-02-131-2/+10
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* Ignore explicit assignments to constants in HDL codeClifford Wolf2015-02-081-0/+14
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* Fixed a bug with autowire bit sizeClifford Wolf2015-02-081-9/+3
| | | | (removed leftover from when we tried to auto-size the wires)
* Added ENABLE_NDEBUG makefile optionsClifford Wolf2015-01-241-0/+2
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* Ignoring more system task and functionsClifford Wolf2015-01-151-1/+3
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* Fixed handling of "input foo; reg [0:0] foo;"Clifford Wolf2015-01-151-0/+7
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* Consolidate "Blocking assignment to memory.." msgs for the same lineClifford Wolf2015-01-151-3/+9
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* Fixed memory->start_offset handlingClifford Wolf2015-01-011-6/+7
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* Added global yosys_celltypesClifford Wolf2014-12-291-1/+1
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* dict/pool changes in astClifford Wolf2014-12-293-16/+24
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* Changed more code to dict<> and pool<>Clifford Wolf2014-12-283-6/+6
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* Fixed mem2reg warning messageClifford Wolf2014-12-271-3/+3
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* Added Yosys::{dict,nodict,vector} container typesClifford Wolf2014-12-262-2/+2
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* Renamed extend() to extend_xx(), changed most users to extend_u0()Clifford Wolf2014-12-241-1/+1
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