| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | read_ilang: do bounds checking on bit indices | Marcin Kościelnicki | 2019-11-27 | 1 | -0/+4 |
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| * | Allow attributes on individual switch cases in RTLIL. | whitequark | 2019-07-08 | 1 | -4/+9 |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The parser changes are slightly awkward. Consider the following IL: process $0 <point 1> switch \foo <point 2> case 1'1 assign \bar \baz <point 3> ... case end end Before this commit, attributes are valid in <point 1>, and <point 3> iff it is immediately followed by a `switch`. (They are essentially attached to the switch.) But, after this commit, and because switch cases do not have an ending delimiter, <point 3> becomes ambiguous: the attribute could attach to either the following `case`, or to the following `switch`. This isn't expressible in LALR(1) and results in a reduce/reduce conflict. To address this, attributes inside processes are now valid anywhere inside the process: in <point 1> and <point 3> a part of case body, and in <point 2> as a separate rule. As a consequence, attributes can now precede `assign`s, which is made illegal in the same way it is illegal to attach attributes to `connect`. Attributes are tracked separately from the parser state, so this does not affect collection of attributes at all, other than allowing them on `case`s. The grammar change serves purely to allow attributes in more syntactic places. | ||||
| * | Make the generated *.tab.hh include all the headers needed to define the union. | Henner Zeller | 2019-05-14 | 1 | -1/+9 |
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| * | Merge pull request #946 from YosysHQ/clifford/specify | Clifford Wolf | 2019-05-06 | 1 | -1/+7 |
| |\ | | | | | Add specify parser | ||||
| | * | Add "real" keyword to ilang format | Clifford Wolf | 2019-05-06 | 1 | -1/+7 |
| | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| * | | Fix the other bison warning in ilang_parser.y | Clifford Wolf | 2019-05-06 | 1 | -1/+1 |
| |/ | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| * | Add "read_ilang -lib" | Clifford Wolf | 2019-04-05 | 1 | -2/+4 |
| | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| * | Add "read_ilang -[no]overwrite" | Clifford Wolf | 2018-12-23 | 1 | -3/+23 |
| | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| * | read_ilang: allow slicing sigspecs. | whitequark | 2018-12-16 | 1 | -10/+6 |
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| * | Added avail params to ilang format, check module params in 'hierarchy -check' | Clifford Wolf | 2016-10-22 | 1 | -1/+7 |
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| * | Added $global_clock verilog syntax support for creating $ff cells | Clifford Wolf | 2016-10-14 | 1 | -1/+7 |
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| * | Fixed oom bug in ilang parser | Clifford Wolf | 2015-11-29 | 1 | -2/+2 |
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| * | Fixed performance bug in ilang parser | Clifford Wolf | 2015-11-27 | 1 | -6/+12 |
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| * | Import more std:: stuff into Yosys namespace | Clifford Wolf | 2015-10-25 | 1 | -1/+1 |
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| * | Adjust makefiles to work with out-of-tree builds | Clifford Wolf | 2015-08-12 | 1 | -1/+1 |
| | | | | | This is based on work done by Larry Doolittle | ||||
| * | Fixed trailing whitespaces | Clifford Wolf | 2015-07-02 | 1 | -2/+2 |
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| * | Fixed memory->start_offset handling | Clifford Wolf | 2015-01-01 | 1 | -0/+3 |
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| * | Added Yosys::{dict,nodict,vector} container types | Clifford Wolf | 2014-12-26 | 1 | -1/+1 |
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| * | Updated lexers & parsers to include prefixes | William Speirs | 2014-10-15 | 1 | -0/+409 |
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index : iCE40/yosys | |
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