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* Replace "ILANG" with "RTLIL" everywhere.whitequark2020-08-261-484/+0
| | | | | | | | | | The only difference between "RTLIL" and "ILANG" is that the latter is the text representation of the former, as opposed to the in-memory graph representation. This distinction serves no purpose but confuses people: it is not obvious that the ILANG backend writes RTLIL graphs. Passes `write_ilang` and `read_ilang` are provided as aliases to `write_rtlil` and `read_rtlil` for compatibility.
* Merge pull request #2006 from jersey99/signed-in-rtlil-wirewhitequark2020-06-041-0/+3
|\ | | | | Preserve 'signed'-ness of a verilog wire through RTLIL
| * Preserve 'signed'-ness of a verilog wire through RTLILVamsi K Vytla2020-04-271-0/+3
| | | | | | | | | | | | | | | | | | As per suggestion made in https://github.com/YosysHQ/yosys/pull/1987, now: RTLIL::wire holds an is_signed field. This is exported in JSON backend This is exported via dump_rtlil command This is read in via ilang_parser
* | frontend: cleanup to use more ID::*, more dict<> instead of map<>Eddie Hung2020-05-041-3/+3
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* ilang, ast: Store parameter order and default value information.Marcelina Koƛcielnicka2020-04-211-2/+9
| | | | Fixes #1819, #1820.
* Clean up pseudo-private member usage in `frontends/ilang/ilang_parser.y`.Alberto Gonzalez2020-04-131-4/+4
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* read_ilang: improve error message for overly long wires.whitequark2020-04-061-0/+3
| | | | Fixes #1838.
* read_ilang: do bounds checking on bit indicesMarcin Koƛcielnicki2019-11-271-0/+4
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* Allow attributes on individual switch cases in RTLIL.whitequark2019-07-081-4/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The parser changes are slightly awkward. Consider the following IL: process $0 <point 1> switch \foo <point 2> case 1'1 assign \bar \baz <point 3> ... case end end Before this commit, attributes are valid in <point 1>, and <point 3> iff it is immediately followed by a `switch`. (They are essentially attached to the switch.) But, after this commit, and because switch cases do not have an ending delimiter, <point 3> becomes ambiguous: the attribute could attach to either the following `case`, or to the following `switch`. This isn't expressible in LALR(1) and results in a reduce/reduce conflict. To address this, attributes inside processes are now valid anywhere inside the process: in <point 1> and <point 3> a part of case body, and in <point 2> as a separate rule. As a consequence, attributes can now precede `assign`s, which is made illegal in the same way it is illegal to attach attributes to `connect`. Attributes are tracked separately from the parser state, so this does not affect collection of attributes at all, other than allowing them on `case`s. The grammar change serves purely to allow attributes in more syntactic places.
* Make the generated *.tab.hh include all the headers needed to define the union.Henner Zeller2019-05-141-1/+9
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* Merge pull request #946 from YosysHQ/clifford/specifyClifford Wolf2019-05-061-1/+7
|\ | | | | Add specify parser
| * Add "real" keyword to ilang formatClifford Wolf2019-05-061-1/+7
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | Fix the other bison warning in ilang_parser.yClifford Wolf2019-05-061-1/+1
|/ | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Add "read_ilang -lib"Clifford Wolf2019-04-051-2/+4
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Add "read_ilang -[no]overwrite"Clifford Wolf2018-12-231-3/+23
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* read_ilang: allow slicing sigspecs.whitequark2018-12-161-10/+6
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* Added avail params to ilang format, check module params in 'hierarchy -check'Clifford Wolf2016-10-221-1/+7
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* Added $global_clock verilog syntax support for creating $ff cellsClifford Wolf2016-10-141-1/+7
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* Fixed oom bug in ilang parserClifford Wolf2015-11-291-2/+2
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* Fixed performance bug in ilang parserClifford Wolf2015-11-271-6/+12
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* Import more std:: stuff into Yosys namespaceClifford Wolf2015-10-251-1/+1
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* Adjust makefiles to work with out-of-tree buildsClifford Wolf2015-08-121-1/+1
| | | | This is based on work done by Larry Doolittle
* Fixed trailing whitespacesClifford Wolf2015-07-021-2/+2
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* Fixed memory->start_offset handlingClifford Wolf2015-01-011-0/+3
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* Added Yosys::{dict,nodict,vector} container typesClifford Wolf2014-12-261-1/+1
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* Updated lexers & parsers to include prefixesWilliam Speirs2014-10-151-0/+409