aboutsummaryrefslogtreecommitdiffstats
path: root/frontends/verilog/const2ast.cc
Commit message (Collapse)AuthorAgeFilesLines
* Fix handling of z_digit "?" and fix optimization of cmp with "z"Clifford Wolf2019-09-131-5/+1
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Fix lexing of integer literals, fixes #1364Clifford Wolf2019-09-121-2/+2
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* RTLIL::S{0,1} -> State::S{0,1}Eddie Hung2019-08-071-12/+12
|
* Fix segfault on failed VERILOG_FRONTEND::const2ast, closes #1131Clifford Wolf2019-06-261-1/+1
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Maintain "is_unsized" state of constantsEddie Hung2019-06-201-6/+6
|
* Added support for unsized constants, fixes #1022Miodrag Milanovic2019-05-271-8/+18
| | | | Includes work from @sumit0190 and @AaronKel
* Convert more log_error() to log_file_error() where possible.Henner Zeller2018-07-201-5/+3
| | | | | Mostly statements that span over multiple lines and haven't been caught with the previous conversion.
* Fixed segfault on invalid verilog constant 1'b_Clifford Wolf2015-09-221-1/+1
|
* Small corrections to const2ast warning messagesClifford Wolf2015-08-171-2/+2
|
* Check base-n literals only contain valid digitsFlorian Zeitz2015-08-171-0/+3
|
* Warn on literals exceeding the specified bit widthFlorian Zeitz2015-08-171-34/+39
|
* Another block of spelling fixesLarry Doolittle2015-08-141-1/+1
| | | | Smaller this time
* Fixed handling of [a-fxz?] in decimal constantsClifford Wolf2015-08-111-2/+7
|
* Fixed trailing whitespacesClifford Wolf2015-07-021-2/+2
|
* Fixed two minor bugs in constant parsingClifford Wolf2014-11-241-1/+5
|
* Added warning for use of 'z' constants in HDLClifford Wolf2014-11-141-1/+9
|
* Moved some stuff to kernel/yosys.{h,cc}, using Yosys:: namespaceClifford Wolf2014-07-311-0/+4
|
* Using log_assert() instead of assert()Clifford Wolf2014-07-281-2/+1
|
* Improved parsing of large integer constantsClifford Wolf2014-06-151-11/+28
|
* Fixed handling of unsized constants in verilog frontendClifford Wolf2014-01-241-2/+2
|
* Major redesign of expr width/sign detecion (verilog/ast frontend)Clifford Wolf2013-07-091-1/+1
|
* Added SAT generator and simple sat_solve commandClifford Wolf2013-06-071-3/+2
|
* initial importClifford Wolf2013-01-051-0/+197
generated by cgit v1.2.3 (git 2.25.1) at 2025-04-18 04:02:57 +0000
n">args); void cmd_error(const std::vector<std::string> &args, size_t argidx, std::string msg); void extra_args(std::vector<std::string> args, size_t argidx, RTLIL::Design *design, bool select = true); static void call(RTLIL::Design *design, std::string command); static void call(RTLIL::Design *design, std::vector<std::string> args); static void call_on_selection(RTLIL::Design *design, const RTLIL::Selection &selection, std::string command); static void call_on_selection(RTLIL::Design *design, const RTLIL::Selection &selection, std::vector<std::string> args); static void call_on_module(RTLIL::Design *design, RTLIL::Module *module, std::string command); static void call_on_module(RTLIL::Design *design, RTLIL::Module *module, std::vector<std::string> args); Pass *next_queued_pass; virtual void run_register(); static void init_register(); static void done_register(); virtual void on_register(); virtual void on_shutdown(); }; struct ScriptPass : Pass { bool block_active, help_mode; RTLIL::Design *active_design; std::string active_run_from, active_run_to; ScriptPass(std::string name, std::string short_help = "** document me **") : Pass(name, short_help) { } virtual void script() = 0; bool check_label(std::string label, std::string info = std::string()); void run(std::string command, std::string info = std::string()); void run_nocheck(std::string command, std::string info = std::string()); void run_script(RTLIL::Design *design, std::string run_from = std::string(), std::string run_to = std::string()); void help_script(); }; struct Frontend : Pass { // for reading of here documents static FILE *current_script_file; static std::string last_here_document; std::string frontend_name; Frontend(std::string name, std::string short_help = "** document me **"); void run_register() override; ~Frontend() override; void execute(std::vector<std::string> args, RTLIL::Design *design) override final; virtual void execute(std::istream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) = 0; static std::vector<std::string> next_args; void extra_args(std::istream *&f, std::string &filename, std::vector<std::string> args, size_t argidx, bool bin_input = false); static void frontend_call(RTLIL::Design *design, std::istream *f, std::string filename, std::string command); static void frontend_call(RTLIL::Design *design, std::istream *f, std::string filename, std::vector<std::string> args); }; struct Backend : Pass { std::string backend_name; Backend(std::string name, std::string short_help = "** document me **"); void run_register() override; ~Backend() override; void execute(std::vector<std::string> args, RTLIL::Design *design) override final; virtual void execute(std::ostream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) = 0; void extra_args(std::ostream *&f, std::string &filename, std::vector<std::string> args, size_t argidx, bool bin_output = false); static void backend_call(RTLIL::Design *design, std::ostream *f, std::string filename, std::string command); static void backend_call(RTLIL::Design *design, std::ostream *f, std::string filename, std::vector<std::string> args); }; // implemented in passes/cmds/select.cc extern void handle_extra_select_args(Pass *pass, const std::vector<std::string> &args, size_t argidx, size_t args_size, RTLIL::Design *design); extern RTLIL::Selection eval_select_args(const vector<string> &args, RTLIL::Design *design); extern void eval_select_op(vector<RTLIL::Selection> &work, const string &op, RTLIL::Design *design); extern std::map<std::string, Pass*> pass_register; extern std::map<std::string, Frontend*> frontend_register; extern std::map<std::string, Backend*> backend_register; YOSYS_NAMESPACE_END #endif