iCE40/yosys - clone of https://github.com/YosysHQ/yosys

	Commit message (Expand)	Author	Age	Files	Lines
*	Fixed some missing "verilog_" in documentation	Rodrigo Alejandro Melo	2019-12-13	1	-1/+1
*	Add check for valid macro names in macro definitions	Clifford Wolf	2019-11-07	1	-7/+11
*	Support SystemVerilog `` extension for macros	Jim Paris	2018-05-17	1	-1/+5
*	Skip spaces around macro arguments	Jim Paris	2018-05-17	1	-0/+1
*	Add support for "yosys -E"	Clifford Wolf	2018-01-07	1	-2/+4
*	Accommodate Windows-style paths during include-file processing.	William D. Jones	2017-11-14	1	-4/+20
*	Minor coding style fix	Clifford Wolf	2017-09-26	1	-1/+1
*	Adding support for string macros and macros with arguments after include	combinatorylogic	2017-09-21	1	-41/+69
*	Add support for `resetall compiler directive	Clifford Wolf	2017-04-26	1	-0/+7
*	Fix verilog pre-processor for multi-level relative includes	Clifford Wolf	2017-03-14	1	-4/+26
*	Added support for macros as include file names	Clifford Wolf	2016-11-28	1	-0/+2
*	Remember global declarations and defines accross read_verilog calls	Clifford Wolf	2016-11-15	1	-1/+14
*	SystemVerilog also has assume(), added implicit -D FORMAL	Clifford Wolf	2015-10-13	1	-1/+2
*	Fixed trailing whitespaces	Clifford Wolf	2015-07-02	1	-3/+3
*	Fixed handling of "//" in filenames in verilog pre-processor	Clifford Wolf	2015-02-14	1	-1/+1
*	Define YOSYS and SYNTHESIS in preproc	Clifford Wolf	2015-01-02	1	-1/+2
*	Re-introduced Yosys::readsome() helper function	Clifford Wolf	2014-10-23	1	-5/+3
*	Replaced readsome() with read() and gcount()	Clifford Wolf	2014-10-15	1	-3/+5
*	Fixed win32 troubles with f.readsome()	Clifford Wolf	2014-10-11	1	-1/+1
*	Added format __attribute__ to stringf()	Clifford Wolf	2014-10-10	1	-1/+1
*	Changed frontend-api from FILE to std::istream	Clifford Wolf	2014-08-23	1	-15/+16
*	Fixed line numbers when using here-doc macros	Clifford Wolf	2014-08-14	1	-4/+9
*	Added support for non-standard """ macro bodies	Clifford Wolf	2014-08-13	1	-1/+12
*	Moved some stuff to kernel/yosys.{h,cc}, using Yosys:: namespace	Clifford Wolf	2014-07-31	1	-0/+4
*	Fixed counting verilog line numbers for "// synopsys translate_off" sections	Clifford Wolf	2014-07-30	1	-1/+1
*	Fixed Verilog pre-processor for files with no trailing newline	Clifford Wolf	2014-07-29	1	-1/+1
*	Using log_assert() instead of assert()	Clifford Wolf	2014-07-28	1	-2/+1
*	Added Verilog support for "`default_nettype none"	Clifford Wolf	2014-02-17	1	-1/+0
*	Fixed parsing of verilog macros at end of line	Clifford Wolf	2014-01-18	1	-1/+1
*	Fixed parsing of non-arg macro calls followed by "("	Clifford Wolf	2013-12-27	1	-1/+7
*	Fixed parsing of macros with no arguments and expansion text starting with "("	Clifford Wolf	2013-12-27	1	-1/+2
*	Added elsif preproc support	Clifford Wolf	2013-12-18	1	-1/+14
*	Added support for macro arguments	Clifford Wolf	2013-12-18	1	-23/+75
*	Fixed O(n^2) performance bug in verilog preprocessor	Clifford Wolf	2013-11-22	1	-1/+1
*	Enable {* .. *} feature per default (removes dependency to REJECT feature in ...	Clifford Wolf	2013-11-22	1	-11/+0
*	Added support for include directories with the new '-I' argument of the	Johann Glaser	2013-08-20	1	-2/+12
*	added option '-Dname[=definition]' to command 'read_verilog'	Johann Glaser	2013-05-19	1	-2/+2
*	initial import	Clifford Wolf	2013-01-05	1	-0/+360