iCE40/yosys - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
*	Fixed Verilog pre-processor for files with no trailing newline	Clifford Wolf	2014-07-29	1	-1/+1
*	Using log_assert() instead of assert()	Clifford Wolf	2014-07-28	1	-2/+1
*	Added Verilog support for "`default_nettype none"	Clifford Wolf	2014-02-17	1	-1/+0
*	Fixed parsing of verilog macros at end of line	Clifford Wolf	2014-01-18	1	-1/+1
*	Fixed parsing of non-arg macro calls followed by "("	Clifford Wolf	2013-12-27	1	-1/+7
*	Fixed parsing of macros with no arguments and expansion text starting with "("	Clifford Wolf	2013-12-27	1	-1/+2
*	Added elsif preproc support	Clifford Wolf	2013-12-18	1	-1/+14
*	Added support for macro arguments	Clifford Wolf	2013-12-18	1	-23/+75
*	Fixed O(n^2) performance bug in verilog preprocessor	Clifford Wolf	2013-11-22	1	-1/+1
*	Enable {* .. *} feature per default (removes dependency to REJECT feature in ...	Clifford Wolf	2013-11-22	1	-11/+0
*	Added support for include directories with the new '-I' argument of the	Johann Glaser	2013-08-20	1	-2/+12
*	added option '-Dname[=definition]' to command 'read_verilog'	Johann Glaser	2013-05-19	1	-2/+2
*	initial import	Clifford Wolf	2013-01-05	1	-0/+360