| Commit message (Expand) | Author | Age | Files | Lines |
|---|
| * | Added $anyseq cell type | Clifford Wolf | 2016-10-14 | 1 | -1/+1 |
| * | Removed $aconst cell type | Clifford Wolf | 2016-08-30 | 1 | -1/+1 |
| * | Removed $predict again | Clifford Wolf | 2016-08-28 | 1 | -7/+1 |
| * | Added read_verilog -norestrict -assume-asserts | Clifford Wolf | 2016-08-26 | 1 | -3/+16 |
| * | Improved verilog parser errors | Clifford Wolf | 2016-08-25 | 1 | -0/+3 |
| * | Fixed bug in parsing real constants | Clifford Wolf | 2016-08-06 | 1 | -4/+4 |
| * | Added $anyconst and $aconst | Clifford Wolf | 2016-07-27 | 1 | -1/+1 |
| * | Fixed a verilog parser memory leak | Clifford Wolf | 2016-07-25 | 1 | -0/+1 |
| * | Fixed parsing of empty positional cell ports | Clifford Wolf | 2016-07-25 | 1 | -2/+31 |
| * | No tristate warning message for "read_verilog -lib" | Clifford Wolf | 2016-07-23 | 1 | -5/+5 |
| * | Added $initstate cell type and vlog function | Clifford Wolf | 2016-07-21 | 1 | -0/+2 |
| * | After reading the SV spec, using non-standard predict() instead of expect() | Clifford Wolf | 2016-07-21 | 1 | -5/+5 |
| * | Added basic support for $expect cells | Clifford Wolf | 2016-07-13 | 1 | -1/+8 |
| * | Allow defining input ports as "input logic" in SystemVerilog | Ruben Undheim | 2016-06-20 | 1 | -2/+2 |
| * | Added support for SystemVerilog packages with localparam definitions | Ruben Undheim | 2016-06-18 | 1 | -0/+29 |
| * | Fixed handling of parameters and const functions in casex/casez pattern | Clifford Wolf | 2016-04-21 | 1 | -2/+6 |
| * | Fixed Verilog parser fix and more similar improvements | Clifford Wolf | 2016-03-15 | 1 | -18/+9 |
| * | Use left-recursive rule for cell_port_list in Verilog parser. | Andrew Becker | 2016-03-15 | 1 | -6/+10 |
| * | Fixed handling of parameters and localparams in functions | Clifford Wolf | 2015-11-11 | 1 | -1/+1 |
| * | Fixed bug in verilog parser | Clifford Wolf | 2015-10-15 | 1 | -1/+1 |
| * | Added support for "parameter" and "localparam" in global context | Clifford Wolf | 2015-10-07 | 1 | -0/+2 |
| * | Fixed detection of "task foo(bar);" syntax error | Clifford Wolf | 2015-09-22 | 1 | -0/+2 |
| * | Adjust makefiles to work with out-of-tree builds | Clifford Wolf | 2015-08-12 | 1 | -1/+1 |
| * | Fixed trailing whitespaces | Clifford Wolf | 2015-07-02 | 1 | -5/+5 |
| * | Added non-std verilog assume() statement | Clifford Wolf | 2015-02-26 | 1 | -2/+8 |
| * | Parser support for complex delay expressions | Clifford Wolf | 2015-02-20 | 1 | -7/+20 |
| * | YosysJS stuff | Clifford Wolf | 2015-02-19 | 1 | -0/+1 |
| * | Improved read_verilog support for empty behavioral statements | Clifford Wolf | 2015-02-10 | 1 | -6/+2 |
| * | Fixed supply0/supply1 with many wires | Clifford Wolf | 2014-12-11 | 1 | -3/+15 |
| * | Added warning for use of 'z' constants in HDL | Clifford Wolf | 2014-11-14 | 1 | -4/+4 |
| * | Fixed parsing of nested verilog concatenation and replicate | Clifford Wolf | 2014-11-12 | 1 | -1/+1 |
| * | Fixed parsing of "module mymod #( parameter foo = 1, bar = 2 ..." | Clifford Wolf | 2014-10-30 | 1 | -4/+5 |
| * | Added support for task and function args in parentheses | Clifford Wolf | 2014-10-27 | 1 | -6/+45 |
| * | Updated lexers & parsers to include prefixes | William Speirs | 2014-10-15 | 1 | -0/+1434 |
