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* Ignore empty parameters in Verilog module instantiationsClaire Xenia Wolf2020-10-011-0/+3
| | | | | | Fixes #2394 Signed-off-by: Claire Xenia Wolf <claire@symbioticeda.com>
* Rewrite multirange arrays sizes [n] as [n-1:0]Lukasz Dalek2020-08-031-2/+11
| | | | Signed-off-by: Lukasz Dalek <ldalek@antmicro.com>
* Use %precedence in verilog_parser.yClaire Wolf2020-07-151-4/+4
| | | | Signed-off-by: Claire Wolf <claire@symbioticeda.com>
* Fix bison warnings for missing %emptyClaire Wolf2020-07-151-59/+52
| | | | Signed-off-by: Claire Wolf <claire@symbioticeda.com>
* Add missing semicolonsKamil Rakoczy2020-07-151-5/+5
| | | | Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
* Fix S/R conflictsKamil Rakoczy2020-07-101-1/+2
| | | | | | This commit fixes S/R conflicts introduced by commit 6f9be93. Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
* Fix R/R conflictsKamil Rakoczy2020-07-101-10/+1
| | | | | | | This commit fixes R/R conflicts introduced by commit 7e83a51. Parameter logic is already defined as part of `param_range_type` rule. Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
* Revert "Revert PRs #2203 and #2244."Kamil Rakoczy2020-07-101-10/+19
| | | | This reverts commit 9c120b89ace6c111aa4677616947d18d980b9c1a.
* Revert PRs #2203 and #2244.whitequark2020-07-091-19/+10
| | | | | | | | This reverts commit 7e83a51fc96495c558a31fc3ca6c1a5ba4764f15. This reverts commit b422f2e4d0b8d5bfa97913d6b9dee488b59fc405. This reverts commit 7cb56f34b06de666935fbda315ce7c7bd45048b3. This reverts commit 6f9be939bd7653b0bdcae93a1033a086a4561b68. This reverts commit 76a34dc5f3a60c89efeaa3378ca0e2700a8aebd2.
* Support logic typed parametersLukasz Dalek2020-07-061-7/+10
| | | | Signed-off-by: Lukasz Dalek <ldalek@antmicro.com>
* Merge pull request #2203 from antmicro/fix-grammarclairexen2020-07-011-4/+10
|\ | | | | Signed and macro grammar update
| * Parse macro call attached semicolon as empty expressionLukasz Dalek2020-06-261-1/+1
| | | | | | | | Signed-off-by: Lukasz Dalek <ldalek@antmicro.com>
| * Fix integer signing grammarLukasz Dalek2020-06-261-3/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This commit fixes signed/unsigned grammar in parameters as defined in SV LRM A2.2.1. Example of correct parameters: parameter integer signed i = 0; parameter integer unsigned i = 0; Example of incorrect parameters: parameter signed integer i = 0; parameter unsigned integer i = 0; Signed-off-by: Lukasz Dalek <ldalek@antmicro.com> Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
* | Merge pull request #2179 from splhack/static-castclairexen2020-07-011-0/+19
|\ \ | | | | | | Support SystemVerilog Static Cast
| * | static cast: support changing size and signednessKazuki Sakamoto2020-06-191-0/+19
| |/ | | | | | | | | | | | | | | | | Support SystemVerilog Static Cast - size - signedness - (type is not supposted yet) Fix #535
* | Merge pull request #2188 from antmicro/missing-operatorswhitequark2020-06-261-2/+43
|\ \ | | | | | | Add logic-assignments operators
| * | Support missing sub-assign and and-assign operatorsKamil Rakoczy2020-06-251-2/+19
| | | | | | | | | | | | Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
| * | Support missing xor-assign operatorLukasz Dalek2020-06-241-1/+9
| | | | | | | | | | | | Signed-off-by: Lukasz Dalek <ldalek@antmicro.com>
| * | Add plus-assignment operatorKamil Rakoczy2020-06-241-1/+9
| | | | | | | | | | | | Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
| * | Add or-assignment operatorKamil Rakoczy2020-06-241-1/+9
| |/ | | | | | | Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
* | Support optional labels at the end of package definitionLukasz Dalek2020-06-241-1/+1
| | | | | | | | Signed-off-by: Lukasz Dalek <ldalek@antmicro.com>
* | Support optional labels at the end of module definitionLukasz Dalek2020-06-241-1/+1
|/ | | | Signed-off-by: Lukasz Dalek <ldalek@antmicro.com>
* MSVC cannot omit operand in conditionalAnonymous Maarten2020-06-171-1/+1
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* Support packed arrays in struct/union.Peter Crozier2020-06-071-5/+5
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* Merge branch 'master' into structPeter Crozier2020-06-031-31/+48
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| * verilog: move attr from simple_behav_stmt to its children to attachEddie Hung2020-05-251-13/+17
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| * verilog: do not warn for attributes on null statementsEddie Hung2020-05-251-2/+0
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| * verilog: handle empty generate statement by removing gen_stmt_or_null...Eddie Hung2020-05-251-7/+8
| | | | | | | | | | ... rule which causes a s/r conflict. Now we get an empty genblock, which should be okay.
| * verilog: fix #2037 by permitting (and freeing) attributes on null stmtEddie Hung2020-05-251-1/+5
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| * Merge pull request #2057 from YosysHQ/eddie/fix_task_attrEddie Hung2020-05-211-11/+9
| |\ | | | | | | verilog: support attributes before (not after) task identifier (but 13 s/r conflicts)
| | * Update frontends/verilog/verilog_parser.yEddie Hung2020-05-211-1/+1
| | | | | | | | | Co-authored-by: Alberto Gonzalez <61295559+boqwxp@users.noreply.github.com>
| | * verilog: attributes before task enable (but 13 s/r conflicts)Eddie Hung2020-05-141-10/+8
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| * | verilog: default to input in sv mode if task/func has no dir ...Eddie Hung2020-05-131-2/+10
| | | | | | | | | | | | otherwise error
| * | verilog: error out when non-ANSI task/func argumentsEddie Hung2020-05-111-1/+5
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* | Allow structs within structs.Peter Crozier2020-05-121-7/+18
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* | Generalise structs and add support for packed unions.Peter Crozier2020-05-121-16/+34
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* | Implement SV structs.Peter Crozier2020-05-081-101/+180
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* Merge pull request #2005 from YosysHQ/claire/fix1990Claire Wolf2020-05-071-2/+2
|\ | | | | Add "nowrshmsk" attribute, fix shift-and-mask bit slice write for signed offset
| * Add AST_SELFSZ and improve handling of bit slicesClaire Wolf2020-05-021-2/+2
| | | | | | | | Signed-off-by: Claire Wolf <claire@symbioticeda.com>
* | Merge pull request #2028 from zachjs/masterEddie Hung2020-05-061-1/+6
|\ \ | | | | | | verilog: allow null gen-if then block
| * | verilog: allow null gen-if then blockZachary Snow2020-05-061-1/+6
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* | Merge pull request #2025 from YosysHQ/eddie/frontend_cleanupEddie Hung2020-05-051-13/+13
|\ \ | | | | | | frontend: cleanup to use more ID::*, more dict<> instead of map<>
| * | frontend: cleanup to use more ID::*, more dict<> instead of map<>Eddie Hung2020-05-041-13/+13
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* | Merge pull request #2024 from YosysHQ/eddie/primitive_srcEddie Hung2020-05-051-1/+3
|\ \ | | | | | | verilog: set src attribute for primitives
| * | verilog: set src attribute for primitivesEddie Hung2020-05-041-1/+3
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* / verilog: fix specify src attributeEddie Hung2020-05-041-18/+20
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* Set Verilog source location for explicit blocks (`begin` ... `end`).Alberto Gonzalez2020-04-171-0/+1
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* Add Verilog source location information to `AST_POSEDGE` and `AST_NEGEDGE` ↵Alberto Gonzalez2020-04-171-0/+2
| | | | nodes.
* Add location information to `AST_CONSTANT` nodes.Alberto Gonzalez2020-04-161-0/+3
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* Merge pull request #1879 from jjj11x/jjj11x/package_declwhitequark2020-04-141-1/+2
|\ | | | | support using previously declared types/localparams/parameters in package
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