iCE40/yosys - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
*	Support packed arrays in struct/union.	Peter Crozier	2020-06-07	1	-5/+5
*	Merge branch 'master' into struct	Peter Crozier	2020-06-03	1	-31/+48
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\| *	verilog: move attr from simple_behav_stmt to its children to attach	Eddie Hung	2020-05-25	1	-13/+17
\| *	verilog: do not warn for attributes on null statements	Eddie Hung	2020-05-25	1	-2/+0
\| *	verilog: handle empty generate statement by removing gen_stmt_or_null...	Eddie Hung	2020-05-25	1	-7/+8
\| *	verilog: fix #2037 by permitting (and freeing) attributes on null stmt	Eddie Hung	2020-05-25	1	-1/+5
\| *	Merge pull request #2057 from YosysHQ/eddie/fix_task_attr	Eddie Hung	2020-05-21	1	-11/+9
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\| \| *	Update frontends/verilog/verilog_parser.y	Eddie Hung	2020-05-21	1	-1/+1
\| \| *	verilog: attributes before task enable (but 13 s/r conflicts)	Eddie Hung	2020-05-14	1	-10/+8
\| * \|	verilog: default to input in sv mode if task/func has no dir ...	Eddie Hung	2020-05-13	1	-2/+10
\| * \|	verilog: error out when non-ANSI task/func arguments	Eddie Hung	2020-05-11	1	-1/+5
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* \|	Allow structs within structs.	Peter Crozier	2020-05-12	1	-7/+18
* \|	Generalise structs and add support for packed unions.	Peter Crozier	2020-05-12	1	-16/+34
* \|	Implement SV structs.	Peter Crozier	2020-05-08	1	-101/+180
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*	Merge pull request #2005 from YosysHQ/claire/fix1990	Claire Wolf	2020-05-07	1	-2/+2
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\| *	Add AST_SELFSZ and improve handling of bit slices	Claire Wolf	2020-05-02	1	-2/+2
* \|	Merge pull request #2028 from zachjs/master	Eddie Hung	2020-05-06	1	-1/+6
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\| * \|	verilog: allow null gen-if then block	Zachary Snow	2020-05-06	1	-1/+6
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* \|	Merge pull request #2025 from YosysHQ/eddie/frontend_cleanup	Eddie Hung	2020-05-05	1	-13/+13
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\| * \|	frontend: cleanup to use more ID::*, more dict<> instead of map<>	Eddie Hung	2020-05-04	1	-13/+13
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* \|	Merge pull request #2024 from YosysHQ/eddie/primitive_src	Eddie Hung	2020-05-05	1	-1/+3
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\| * \|	verilog: set src attribute for primitives	Eddie Hung	2020-05-04	1	-1/+3
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* /	verilog: fix specify src attribute	Eddie Hung	2020-05-04	1	-18/+20
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*	Set Verilog source location for explicit blocks (`begin` ... `end`).	Alberto Gonzalez	2020-04-17	1	-0/+1
*	Add Verilog source location information to `AST_POSEDGE` and `AST_NEGEDGE` no...	Alberto Gonzalez	2020-04-17	1	-0/+2
*	Add location information to `AST_CONSTANT` nodes.	Alberto Gonzalez	2020-04-16	1	-0/+3
*	Merge pull request #1879 from jjj11x/jjj11x/package_decl	whitequark	2020-04-14	1	-1/+2
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\| *	support using previously declared types/localparams/params in package	Jeff Wang	2020-04-07	1	-1/+2
* \|	verilog: Fix write to deleted object	David Shah	2020-04-12	1	-1/+0
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*	kernel: big fat patch to use more ID::, otherwise ID()	Eddie Hung	2020-04-02	1	-5/+5
*	kernel: use more ID::*	Eddie Hung	2020-04-02	1	-22/+22
*	verilog: Add location info for generate constructs	David Shah	2020-04-01	1	-0/+6
*	Inline productions to follow house style.	Peter Crozier	2020-03-27	1	-33/+29
*	Error duplicate declarations of a typedef name in the same scope.	Peter Crozier	2020-03-24	1	-2/+10
*	Support module/package/interface/block scope for typedef names.	Peter Crozier	2020-03-23	1	-15/+36
*	Clear pkg_user_types if no packages following a 'design -reset-vlog'.	Peter	2020-03-22	1	-0/+1
*	Parser changes to support typedef.	Peter	2020-03-22	1	-8/+37
*	Merge pull request #1775 from huaixv/asserts_locations	N. Engelhardt	2020-03-19	1	-7/+30
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\| *	Add precise locations for asserts	huaixv	2020-03-19	1	-7/+30
* \|	Add AST node source location information in a couple more parser rules.	Alberto Gonzalez	2020-03-17	1	-0/+2
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*	Merge pull request #1759 from zeldin/constant_with_comment_redux	Miodrag Milanović	2020-03-14	1	-11/+20
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\| *	refixed parsing of constant with comment between size and value	Marcus Comstedt	2020-03-11	1	-11/+20
* \|	verilog: also set location for simple_behavioral_stmt	Eddie Hung	2020-03-10	1	-0/+4
* \|	Set AST source locations in more parser rules.	Alberto Gonzalez	2020-03-10	1	-2/+49
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*	Fix partsel expr bit width handling and add test case	Claire Wolf	2020-03-08	1	-4/+6
*	Fix bison warning for "pure-parser" option	Claire Wolf	2020-03-03	1	-1/+1
*	Closes #1717. Add more precise Verilog source location information to AST and...	Alberto Gonzalez	2020-02-23	1	-11/+77
*	Merge pull request #1703 from YosysHQ/eddie/specify_improve	Eddie Hung	2020-02-21	1	-28/+80
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\| *	verilog: add support for more delays than just rise/fall	Eddie Hung	2020-02-19	1	-1/+40
\| *	verilog: ignore ranges too without -specify	Eddie Hung	2020-02-13	1	-1/+2