| Commit message (Expand) | Author | Age | Files | Lines |
* | kernel: require \B_SIGNED=0 on $shl, $sshl, $shr, $sshr. | whitequark | 2019-12-04 | 1 | -5/+5 |
* | sv: Correct parsing of always_comb, always_ff and always_latch | David Shah | 2019-11-21 | 1 | -2/+37 |
* | Use "(id)" instead of "id" for types as temporary hack | Clifford Wolf | 2019-10-14 | 1 | -11/+69 |
|\ |
|
| * | sv: Disambiguate interface ports | David Shah | 2019-10-03 | 1 | -3/+19 |
| * | sv: Fix memories of typedefs | David Shah | 2019-10-03 | 1 | -1/+1 |
| * | sv: Add %expect | David Shah | 2019-10-03 | 1 | -0/+1 |
| * | sv: Add support for memory typedefs | David Shah | 2019-10-03 | 1 | -1/+19 |
| * | sv: Fix typedef parameters | David Shah | 2019-10-03 | 1 | -4/+17 |
| * | sv: Switch parser to glr, prep for typedef | David Shah | 2019-10-03 | 1 | -4/+34 |
|/ |
|
* | substr() -> compare() | Eddie Hung | 2019-08-07 | 1 | -4/+4 |
* | Some cleanups in "ignore specify parser" | Clifford Wolf | 2019-07-03 | 1 | -79/+5 |
* | Improve specify dummy parser, fixes #1144 | Clifford Wolf | 2019-06-28 | 1 | -2/+9 |
* | Make genvar a signed type | Eddie Hung | 2019-06-20 | 1 | -0/+1 |
* | Merge branch 'unpacked_arrays' of https://github.com/towoe/yosys-sv into towo... | Clifford Wolf | 2019-06-20 | 1 | -1/+7 |
|\ |
|
| * | Unpacked array declaration using size | Tobias Wölfel | 2019-06-19 | 1 | -1/+7 |
* | | Add "read_verilog -pwires" feature, closes #1106 | Clifford Wolf | 2019-06-19 | 1 | -2/+6 |
* | | Add defaultvalue attribute | Clifford Wolf | 2019-06-19 | 1 | -0/+11 |
* | | Fix handling of "logic" variables with initial value | Clifford Wolf | 2019-06-19 | 1 | -2/+2 |
* | | Fixed brojen $error()/$info/$warning() on non-generate blocks | Udi Finkelstein | 2019-06-11 | 1 | -2/+12 |
|/ |
|
* | Merge branch 'pr_elab_sys_tasks' of https://github.com/udif/yosys into cliffo... | Clifford Wolf | 2019-06-07 | 1 | -1/+10 |
|\ |
|
| * | Initial implementation of elaboration system tasks | Udi Finkelstein | 2019-05-03 | 1 | -1/+10 |
* | | Cleanup tux3-implicit_named_connection | Clifford Wolf | 2019-06-07 | 1 | -1/+1 |
* | | Merge branch 'implicit_named_connection' of https://github.com/tux3/yosys int... | Clifford Wolf | 2019-06-07 | 1 | -1/+10 |
|\ \ |
|
| * | | SystemVerilog support for implicit named port connections | tux3 | 2019-06-06 | 1 | -9/+17 |
* | | | Fixed memory leak. | Maciej Kurc | 2019-06-05 | 1 | -0/+4 |
* | | | Added support for parsing attributes on port connections. | Maciej Kurc | 2019-05-31 | 1 | -10/+10 |
|/ / |
|
* | | fix indentation across files | Stefan Biereigel | 2019-05-23 | 1 | -2/+2 |
* | | make lexer/parser aware of wand/wor net types | Stefan Biereigel | 2019-05-23 | 1 | -1/+7 |
* | | Merge pull request #1013 from antmicro/parameter_attributes | Clifford Wolf | 2019-05-16 | 1 | -2/+2 |
|\ \ |
|
| * | | Added support for parsing attributes on parameters in Verilog frontent. Conte... | Maciej Kurc | 2019-05-16 | 1 | -2/+2 |
* | | | Make the generated *.tab.hh include all the headers needed to define the union. | Henner Zeller | 2019-05-14 | 1 | -1/+9 |
|/ / |
|
* | | Merge pull request #946 from YosysHQ/clifford/specify | Clifford Wolf | 2019-05-06 | 1 | -22/+295 |
|\ \ |
|
| * \ | Merge branch 'master' of github.com:YosysHQ/yosys into clifford/specify | Clifford Wolf | 2019-05-06 | 1 | -2/+8 |
| |\ \ |
|
| * | | | Improve $specrule interface | Clifford Wolf | 2019-04-23 | 1 | -8/+18 |
| * | | | Improve $specrule interface | Clifford Wolf | 2019-04-23 | 1 | -20/+18 |
| * | | | Add $specrule cells for $setup/$hold/$skew specify rules | Clifford Wolf | 2019-04-23 | 1 | -2/+67 |
| * | | | Rename T_{RISE,FALL}_AVG to T_{RISE,FALL}_TYP to better match verilog std nom... | Clifford Wolf | 2019-04-23 | 1 | -2/+2 |
| * | | | Add specify parser | Clifford Wolf | 2019-04-23 | 1 | -22/+222 |
| | |/
| |/| |
|
* | | | verilog_parser: Fix Bison warning | Ben Widawsky | 2019-05-05 | 1 | -1/+1 |
| |/
|/| |
|
* | | Merge pull request #988 from YosysHQ/clifford/fix987 | Clifford Wolf | 2019-05-04 | 1 | -1/+4 |
|\ \ |
|
| * | | Add approximate support for SV "var" keyword, fixes #987 | Clifford Wolf | 2019-05-04 | 1 | -1/+4 |
| |/ |
|
* / | Add support for SVA "final" keyword | Clifford Wolf | 2019-05-04 | 1 | -1/+4 |
|/ |
|
* | New behavior for front-end handling of whiteboxes | Clifford Wolf | 2019-04-20 | 1 | -5/+5 |
* | Add "whitebox" attribute, add "read_verilog -wb" | Clifford Wolf | 2019-04-18 | 1 | -5/+5 |
* | Fix handling of cases that look like sva labels, fixes #862 | Clifford Wolf | 2019-03-10 | 1 | -43/+56 |
* | Also add support for labels on sva module items, fixes #699 | Clifford Wolf | 2019-03-08 | 1 | -39/+61 |
* | Add support for SVA labels in read_verilog | Clifford Wolf | 2019-03-07 | 1 | -23/+79 |
* | Fix typographical and grammatical errors and inconsistencies. | whitequark | 2019-01-02 | 1 | -3/+3 |
* | verilog_parser: Properly handle recursion when processing attributes | Sylvain Munaut | 2018-12-14 | 1 | -19/+29 |
* | Add warning for SV "restrict" without "property" | Clifford Wolf | 2018-11-04 | 1 | -2/+11 |