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* Closes #1717. Add more precise Verilog source location information to AST ↵Alberto Gonzalez2020-02-234-32/+131
| | | | and RTLIL nodes.
* Merge pull request #1703 from YosysHQ/eddie/specify_improveEddie Hung2020-02-212-29/+81
|\ | | | | Improve specify parser
| * verilog: add support for more delays than just rise/fallEddie Hung2020-02-191-1/+40
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| * verilog: ignore ranges too without -specifyEddie Hung2020-02-131-1/+2
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| * verilog: improve specify support when not in -specify modeEddie Hung2020-02-131-13/+7
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| * verilog: ignore '&&&' when not in -specify modeEddie Hung2020-02-132-5/+6
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| * specify: system timing checks to accept min:typ:max tripleEddie Hung2020-02-131-12/+29
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* | Merge pull request #1642 from jjj11x/jjj11x/sv-enumClaire Wolf2020-02-201-2/+104
|\ \ | |/ |/| Enum support
| * add attributes for enumerated values in ilangJeff Wang2020-02-171-1/+8
| | | | | | | | | | | | - information also useful for strongly-typed enums (not implemented) - resolves enum values in ilang part of #1594 - still need to output enums to VCD (or better yet FST) files
| * lexer doesn't seem to return TOK_REG for logic anymoreJeff Wang2020-01-161-3/+4
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| * allow enum typedefsJeff Wang2020-01-161-1/+6
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| * partial rebase of PeterCrozier's enum work onto current masterJeff Wang2020-01-161-1/+90
| | | | | | | | | | | | | | | | | | | | | | I tried to keep only the enum-related changes, and minimize the diff. (The original commit also had a lot of work done to get typedefs working, but yosys has diverged quite a bit since the 2018-03-09 commit, with a new typedef implementation.) I did not include the import related changes either. Original commit: "Initial implementation of enum, typedef, import. Still a WIP." https://github.com/PeterCrozier/yosys/commit/881833aa738e7404987646ea8076284e911fce3f
* | Merge pull request #1679 from thasti/delay-parsingN. Engelhardt2020-02-131-2/+2
|\ \ | | | | | | Fix crash on wire declaration with delay
| * | correct wire declaration grammar for #1614Stefan Biereigel2020-02-031-2/+2
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* | sv: Improve handling of wildcard port connectionsDavid Shah2020-02-022-4/+6
| | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | hierarchy: Resolve SV wildcard port connectionsDavid Shah2020-02-021-1/+1
| | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | sv: Add lexing and parsing of .* (wildcard port conns)David Shah2020-02-022-1/+6
|/ | | | Signed-off-by: David Shah <dave@ds0.me>
* Fixed some missing "verilog_" in documentationRodrigo Alejandro Melo2019-12-132-2/+2
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* kernel: require \B_SIGNED=0 on $shl, $sshl, $shr, $sshr.whitequark2019-12-041-5/+5
| | | | | | | Before this commit, these cells would accept any \B_SIGNED and in case of \B_SIGNED=1, would still treat the \B input as unsigned. Also fix the Verilog frontend to never emit such constructs.
* sv: Correct parsing of always_comb, always_ff and always_latchDavid Shah2019-11-212-5/+40
| | | | Signed-off-by: David Shah <dave@ds0.me>
* Add check for valid macro names in macro definitionsClifford Wolf2019-11-071-7/+11
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Add "verilog_defines -list" and "verilog_defines -reset"Clifford Wolf2019-10-211-0/+16
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Use "(id)" instead of "id" for types as temporary hackClifford Wolf2019-10-141-11/+69
|\ | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * sv: Disambiguate interface portsDavid Shah2019-10-031-3/+19
| | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
| * sv: Fix memories of typedefsDavid Shah2019-10-031-1/+1
| | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
| * sv: Add %expectDavid Shah2019-10-031-0/+1
| | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
| * sv: Add support for memory typedefsDavid Shah2019-10-031-1/+19
| | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
| * sv: Fix typedef parametersDavid Shah2019-10-031-4/+17
| | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
| * sv: Switch parser to glr, prep for typedefDavid Shah2019-10-031-4/+34
|/ | | | Signed-off-by: David Shah <dave@ds0.me>
* Fix handling of z_digit "?" and fix optimization of cmp with "z"Clifford Wolf2019-09-131-5/+1
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Fix lexing of integer literals without radixClifford Wolf2019-09-131-1/+1
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Fix lexing of integer literals, fixes #1364Clifford Wolf2019-09-122-3/+3
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* substr() -> compare()Eddie Hung2019-08-071-4/+4
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* RTLIL::S{0,1} -> State::S{0,1}Eddie Hung2019-08-071-12/+12
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* verilog_lexer: Increase YY_BUF_SIZE to 65536David Shah2019-07-261-0/+3
| | | | Signed-off-by: David Shah <dave@ds0.me>
* Merge pull request #1147 from YosysHQ/clifford/fix1144Clifford Wolf2019-07-031-81/+14
|\ | | | | Improve specify dummy parser
| * Some cleanups in "ignore specify parser"Clifford Wolf2019-07-031-79/+5
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * Improve specify dummy parser, fixes #1144Clifford Wolf2019-06-281-2/+9
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | Fix read_verilog assert/assume/etc on default case label, fixes ↵Clifford Wolf2019-07-021-0/+2
|/ | | | | | YosysHQ/SymbiYosys#53 Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Fix segfault on failed VERILOG_FRONTEND::const2ast, closes #1131Clifford Wolf2019-06-261-1/+1
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Merge pull request #1119 from YosysHQ/eddie/fix1118Clifford Wolf2019-06-211-0/+1
|\ | | | | Make genvar a signed type
| * Make genvar a signed typeEddie Hung2019-06-201-0/+1
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* | Maintain "is_unsized" state of constantsEddie Hung2019-06-201-6/+6
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* Merge branch 'unpacked_arrays' of https://github.com/towoe/yosys-sv into ↵Clifford Wolf2019-06-201-1/+7
|\ | | | | | | towoe-unpacked_arrays
| * Unpacked array declaration using sizeTobias Wölfel2019-06-191-1/+7
| | | | | | | | | | | | | | | | Allows fixed-sized array dimension specified by a single number. This commit is based on the work from PeterCrozier https://github.com/YosysHQ/yosys/pull/560. But is split out of the original work.
* | Add "read_verilog -pwires" feature, closes #1106Clifford Wolf2019-06-192-3/+15
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | Add defaultvalue attributeClifford Wolf2019-06-191-0/+11
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | Fix handling of "logic" variables with initial valueClifford Wolf2019-06-191-2/+2
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | Fixed brojen $error()/$info/$warning() on non-generate blocksUdi Finkelstein2019-06-112-3/+13
|/ | | | (within always/initial blocks)
* Merge branch 'pr_elab_sys_tasks' of https://github.com/udif/yosys into ↵Clifford Wolf2019-06-072-1/+15
|\ | | | | | | clifford/pr983
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