iCE40/yosys - [no description]

	Commit message (Collapse)	Author	Age	Files	Lines
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*	Improved error message for options after front-end filename arguments	Clifford Wolf	2014-06-04	1	-1/+1
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*	Fixed clang -Wdeprecated-register warnings	Clifford Wolf	2014-04-20	1	-0/+5
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*	Replaced depricated %name-prefix= bison directive	Clifford Wolf	2014-04-20	1	-1/+1
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*	Merged OSX fixes from Siesh1oo with some modifications	Clifford Wolf	2014-03-13	1	-0/+1
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*	Added support for `line compiler directive	Clifford Wolf	2014-03-11	1	-0/+11
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*	Added Verilog support for "`default_nettype none"	Clifford Wolf	2014-02-17	5	-2/+18
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*	Added a warning note about error reporting to read_verilog help message	Clifford Wolf	2014-02-16	1	-0/+5
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*	Implemented read_verilog -defer	Clifford Wolf	2014-02-13	1	-1/+11
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*	Added support for functions returning integer	Clifford Wolf	2014-02-12	1	-2/+12
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*	Added read_verilog -setattr	Clifford Wolf	2014-02-05	1	-0/+15
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*	Added support for blanks after -I and -D in read_verilog	Clifford Wolf	2014-02-02	1	-7/+20
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*	Added constant size expression support of sized constants	Clifford Wolf	2014-02-01	1	-0/+22
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*	Added read_verilog -icells option	Clifford Wolf	2014-01-29	1	-1/+9
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*	Fixed handling of unsized constants in verilog frontend	Clifford Wolf	2014-01-24	1	-2/+2
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*	Added Verilog parser support for asserts	Clifford Wolf	2014-01-19	2	-3/+10
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*	Fixed parsing of verilog macros at end of line	Clifford Wolf	2014-01-18	1	-1/+1
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*	Added verilog_defaults command	Clifford Wolf	2014-01-17	1	-0/+66
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*	Fixed parsing of non-arg macro calls followed by "("	Clifford Wolf	2013-12-27	1	-1/+7
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*	Fixed parsing of macros with no arguments and expansion text starting with "("	Clifford Wolf	2013-12-27	1	-1/+2
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*	Added proper === and !== support in constant expressions	Clifford Wolf	2013-12-27	2	-3/+11
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*	Added elsif preproc support	Clifford Wolf	2013-12-18	1	-1/+14
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*	Added support for macro arguments	Clifford Wolf	2013-12-18	1	-23/+75
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*	Added AstNode::mkconst_str API	Clifford Wolf	2013-12-05	1	-12/+1
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*	Various improvements in support for generate statements	Clifford Wolf	2013-12-04	2	-5/+43
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*	Added support for local regs in named blocks	Clifford Wolf	2013-12-04	1	-2/+5
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*	Added verilog frontend -ignore_redef option	Clifford Wolf	2013-11-24	1	-1/+10
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*	Improved handling of initialized registers	Clifford Wolf	2013-11-23	1	-10/+10
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*	Renamed "placeholder" to "blackbox"	Clifford Wolf	2013-11-22	1	-1/+1
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*	Fixed O(n^2) performance bug in verilog preprocessor	Clifford Wolf	2013-11-22	1	-1/+1
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*	Enable {* .. *} feature per default (removes dependency to REJECT feature in ↵	Clifford Wolf	2013-11-22	4	-22/+2
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*	Implemented indexed part selects	Clifford Wolf	2013-11-20	2	-0/+14
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*	Added "synthesis" in (synopsys\|synthesis) comment support	Clifford Wolf	2013-11-20	1	-6/+6
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*	Implemented part/bit select on memory read	Clifford Wolf	2013-11-20	1	-2/+12
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*	Added init= attribute for fpga-style reset values	Clifford Wolf	2013-11-20	1	-6/+19
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*	Fixed parsing of module arguments when one type is used for many args	Clifford Wolf	2013-11-19	1	-3/+10
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*	Fixed parsing of "parameter integer"	Clifford Wolf	2013-11-13	1	-2/+2
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*	Various fixes for correct parameter support	Clifford Wolf	2013-11-07	1	-26/+52
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*	Fixed handling of boolean attributes (frontends)	Clifford Wolf	2013-10-24	1	-2/+2
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*	Fixed handling of boolean attributes (kernel)	Clifford Wolf	2013-10-24	1	-1/+1
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*	fixed Verilog parser filename and line numbering issue with include files	Johann Glaser	2013-08-21	1	-0/+2
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*	Added support for include directories with the new '-I' argument of the	Johann Glaser	2013-08-20	3	-4/+24
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*	Added support for notif0/notif1 primitives	Johann Glaser	2013-08-20	1	-1/+1
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*	Added support for bufif0/bufif1 primitives	Clifford Wolf	2013-08-19	1	-1/+1
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*	Improved ast dumping (ast/verilog frontend)	Clifford Wolf	2013-08-19	1	-12/+11
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*	Major redesign of expr width/sign detecion (verilog/ast frontend)	Clifford Wolf	2013-07-09	1	-1/+1
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*	Added defparam support to Verilog/AST frontend	Clifford Wolf	2013-07-04	2	-10/+41
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*	More fixes for bugs found using xsthammer	Clifford Wolf	2013-06-13	2	-4/+14
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*	Further improved and extended xsthammer	Clifford Wolf	2013-06-11	1	-0/+1
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*	Enabled AST/Verilog front-end optimizations per default	Clifford Wolf	2013-06-10	1	-1/+10
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*	Added SAT generator and simple sat_solve command	Clifford Wolf	2013-06-07	2	-3/+4
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