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* Small corrections to const2ast warning messagesClifford Wolf2015-08-171-2/+2
* Check base-n literals only contain valid digitsFlorian Zeitz2015-08-171-0/+3
* Warn on literals exceeding the specified bit widthFlorian Zeitz2015-08-171-34/+39
* Another block of spelling fixesLarry Doolittle2015-08-142-3/+3
* Re-created command-reference-manual.tex, copied some doc fixes to online helpClifford Wolf2015-08-141-6/+6
* Spell check (by Larry Doolittle)Clifford Wolf2015-08-141-1/+1
* Adjust makefiles to work with out-of-tree buildsClifford Wolf2015-08-123-4/+6
* Fixed handling of [a-fxz?] in decimal constantsClifford Wolf2015-08-111-2/+7
* Add -noautowire option to verilog frontendMarcus Comstedt2015-08-011-1/+8
* Fixed trailing whitespacesClifford Wolf2015-07-026-16/+16
* Verilog front-end: define `BLACKBOX in -lib modeClifford Wolf2015-04-191-1/+2
* Ignore celldefine directive in verilog front-endClifford Wolf2015-03-251-0/+3
* Added non-std verilog assume() statementClifford Wolf2015-02-264-5/+25
* Parser support for complex delay expressionsClifford Wolf2015-02-201-7/+20
* YosysJS stuffClifford Wolf2015-02-191-0/+1
* Added "read_verilog -nomeminit" and "nomeminit" attributeClifford Wolf2015-02-141-1/+15
* Fixed handling of "//" in filenames in verilog pre-processorClifford Wolf2015-02-142-1/+5
* Improved read_verilog support for empty behavioral statementsClifford Wolf2015-02-101-6/+2
* Ignoring more system task and functionsClifford Wolf2015-01-151-1/+1
* Enable bison to be customizedFabio Utzig2015-01-081-1/+1
* Define YOSYS and SYNTHESIS in preprocClifford Wolf2015-01-021-1/+2
* Improved some warning messagesClifford Wolf2014-12-271-6/+18
* Fixed supply0/supply1 with many wiresClifford Wolf2014-12-111-3/+15
* Fixed minor bug in parsing delaysClifford Wolf2014-11-241-1/+4
* Fixed two minor bugs in constant parsingClifford Wolf2014-11-242-3/+7
* Added warning for use of 'z' constants in HDLClifford Wolf2014-11-143-6/+14
* Fixed parsing of nested verilog concatenation and replicateClifford Wolf2014-11-121-1/+1
* Added log_warning() APIClifford Wolf2014-11-091-6/+6
* Fixed parsing of "module mymod #( parameter foo = 1, bar = 2 ..."Clifford Wolf2014-10-301-4/+5
* Added support for task and function args in parenthesesClifford Wolf2014-10-271-6/+45
* Re-introduced Yosys::readsome() helper functionClifford Wolf2014-10-232-10/+4
* Print "SystemVerilog" in "read_verilog -sv" log messagesClifford Wolf2014-10-161-1/+1
* Updated .gitignore file for ilang and verilog frontendsClifford Wolf2014-10-151-4/+4
* Replaced readsome() with read() and gcount()Clifford Wolf2014-10-151-3/+5
* Updated lexers & parsers to include prefixesWilliam Speirs2014-10-153-14/+18
* Fixed win32 troubles with f.readsome()Clifford Wolf2014-10-112-2/+2
* Added format __attribute__ to stringf()Clifford Wolf2014-10-101-1/+1
* Renamed SIZE() to GetSize() because of name collision on Win32Clifford Wolf2014-10-101-1/+1
* namespace YosysClifford Wolf2014-09-271-16/+16
* Removed compatbility.{h,cc}: Not using open_memstream/fmemopen anymoreClifford Wolf2014-08-231-4/+1
* Changed frontend-api from FILE to std::istreamClifford Wolf2014-08-235-22/+30
* Added support for non-standard <plugin>:<c_name> DPI syntaxClifford Wolf2014-08-221-0/+12
* Added support for DPI function with different names in C and VerilogClifford Wolf2014-08-212-5/+16
* Added Verilog/AST support for DPI functions (dpi_call() still unimplemented)Clifford Wolf2014-08-212-1/+54
* Added support for global tasks and functionsClifford Wolf2014-08-212-15/+23
* Added "via_celltype" attribute on task/funcClifford Wolf2014-08-181-12/+14
* Fixed line numbers when using here-doc macrosClifford Wolf2014-08-141-4/+9
* Added support for non-standard """ macro bodiesClifford Wolf2014-08-131-1/+12
* Also allow "module foobar(input foo, output bar, ...);" syntaxClifford Wolf2014-08-071-3/+5
* Added AST_MULTIRANGE (arrays with more than 1 dimension)Clifford Wolf2014-08-061-4/+18
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