| Commit message (Collapse) | Author | Age | Files | Lines | ||
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| * | | | Merge remote-tracking branch 'origin/read_aiger' into xaig | Eddie Hung | 2019-02-13 | 1 | -10/+3 | |
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| | * | | Merge branch 'read_aiger' of github.com:eddiehung/yosys into read_aiger | Eddie Hung | 2019-02-12 | 1 | -3/+1 | |
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| | | * | | Do not break for constraints | Eddie Hung | 2019-02-11 | 1 | -1/+0 | |
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| | | * | | No increment line_count for binary ANDs | Eddie Hung | 2019-02-11 | 1 | -1/+1 | |
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| | | * | | Do not ignore newline after AND in binary AIG | Eddie Hung | 2019-02-11 | 1 | -1/+0 | |
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| | * | | | Use module->add{Not,And}Gate() functions | Eddie Hung | 2019-02-12 | 1 | -8/+2 | |
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| * | | | Merge https://github.com/YosysHQ/yosys into xaig | Eddie Hung | 2019-02-13 | 1 | -5/+4 | |
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| | * | | Fix sign handling of real constants | Clifford Wolf | 2019-02-13 | 1 | -5/+4 | |
| | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | | | Add support for read_aiger -wideports | Eddie Hung | 2019-02-12 | 2 | -6/+15 | |
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| * | | | Add support for read_aiger -map | Eddie Hung | 2019-02-12 | 2 | -4/+82 | |
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| * | | | Parse 'm' in xaiger | Eddie Hung | 2019-02-12 | 1 | -20/+57 | |
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| * | | | Add read_xaiger | Eddie Hung | 2019-02-11 | 2 | -27/+108 | |
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| * | | addDff -> addDffGate as per @daveshah1 | Eddie Hung | 2019-02-08 | 1 | -1/+1 | |
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| * | | Fix tabulation | Eddie Hung | 2019-02-08 | 1 | -28/+28 | |
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| * | | -module_name arg to go before -clk_name | Eddie Hung | 2019-02-08 | 1 | -7/+7 | |
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| * | | Add missing "[options]" to read_blif help | Eddie Hung | 2019-02-08 | 1 | -1/+1 | |
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| * | | Allow module name to be determined by argument too | Eddie Hung | 2019-02-08 | 2 | -14/+44 | |
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| * | | Refactor into AigerReader class | Eddie Hung | 2019-02-08 | 2 | -79/+92 | |
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| * | | Parse binary AIG files | Eddie Hung | 2019-02-08 | 1 | -49/+164 | |
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| * | | Refactor to parse_aiger_header() | Eddie Hung | 2019-02-08 | 1 | -26/+32 | |
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| * | | Add comment | Eddie Hung | 2019-02-08 | 1 | -0/+1 | |
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| * | | Handle reset logic in latches | Eddie Hung | 2019-02-08 | 1 | -2/+17 | |
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| * | | Change literal vars from int to unsigned | Eddie Hung | 2019-02-08 | 1 | -1/+1 | |
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| * | | Create clk outside of latch loop | Eddie Hung | 2019-02-08 | 1 | -7/+9 | |
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| * | | Handle latch symbols too | Eddie Hung | 2019-02-08 | 1 | -3/+1 | |
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| * | | Remove return after log_error | Eddie Hung | 2019-02-08 | 1 | -27/+9 | |
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| * | | Add support for symbol tables | Eddie Hung | 2019-02-08 | 1 | -1/+49 | |
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| * | | Stub for binary AIGER | Eddie Hung | 2019-02-08 | 1 | -3/+8 | |
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| * | | Refactor | Eddie Hung | 2019-02-06 | 1 | -1/+8 | |
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| * | | WIP | Eddie Hung | 2019-02-06 | 3 | -0/+247 | |
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| * | Bugfix in Verilog string handling | Clifford Wolf | 2019-01-05 | 1 | -1/+1 | |
| | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | Remove -m32 Verific eval lib build instructions | Clifford Wolf | 2019-01-04 | 1 | -29/+0 | |
| | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | Improve VerificImporter support for writes to asymmetric memories | Clifford Wolf | 2019-01-02 | 1 | -22/+35 | |
| | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | Fix VerificImporter asymmetric memories error message | Clifford Wolf | 2019-01-02 | 1 | -1/+1 | |
| | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | Fix typographical and grammatical errors and inconsistencies. | whitequark | 2019-01-02 | 5 | -11/+11 | |
| | | | | | | | | | | | | | The initial list of hits was generated with the codespell command below, and each hit was evaluated and fixed manually while taking context into consideration. DIRS="kernel/ frontends/ backends/ passes/ techlibs/" DIRS="${DIRS} libs/ezsat/ libs/subcircuit" codespell $DIRS -S *.o -L upto,iff,thru,synopsys,uint More hits were found by looking through comments and strings manually. | |||||
| * | Add "read_ilang -[no]overwrite" | Clifford Wolf | 2018-12-23 | 3 | -4/+54 | |
| | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | Fix segfault in AST simplify | Clifford Wolf | 2018-12-18 | 1 | -0/+5 | |
| | | | | | | | (as proposed by Dan Gisselquist) Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | Improve src tagging (using names and attrs) of cells and wires in verific ↵ | Clifford Wolf | 2018-12-18 | 2 | -99/+160 | |
| | | | | | | | front-end Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | read_ilang: allow slicing sigspecs. | whitequark | 2018-12-16 | 1 | -10/+6 | |
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| * | verilog_parser: Properly handle recursion when processing attributes | Sylvain Munaut | 2018-12-14 | 1 | -19/+29 | |
| | | | | | | | Fixes #737 Signed-off-by: Sylvain Munaut <tnt@246tNt.com> | |||||
| * | Verific updates | Clifford Wolf | 2018-12-06 | 1 | -53/+0 | |
| | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | Make return value of $clog2 signed | Sylvain Munaut | 2018-11-24 | 1 | -1/+1 | |
| | | | | | | | | | As per Verilog 2005 - 17.11.1. Fixes #708 Signed-off-by: Sylvain Munaut <tnt@246tNt.com> | |||||
| * | Set Verific flag vhdl_support_variable_slice=1 | Clifford Wolf | 2018-11-09 | 1 | -0/+1 | |
| | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | Allow square brackets in liberty identifiers | Clifford Wolf | 2018-11-05 | 1 | -1/+2 | |
| | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | Add warning for SV "restrict" without "property" | Clifford Wolf | 2018-11-04 | 1 | -2/+11 | |
| | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | Various indenting fixes in AST front-end (mostly space vs tab issues) | Clifford Wolf | 2018-11-04 | 3 | -99/+69 | |
| | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | Make and dependent upon LSB only | ZipCPU | 2018-11-03 | 1 | -2/+8 | |
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| * | Do not generate "reg assigned in a continuous assignment" warnings for "rand ↵ | Clifford Wolf | 2018-11-01 | 1 | -2/+15 | |
| | | | | | | | reg" Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | Fix minor typo in error message | Clifford Wolf | 2018-10-25 | 1 | -1/+1 | |
| | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | Merge pull request #679 from udif/pr_syntax_error | Clifford Wolf | 2018-10-25 | 1 | -14/+14 | |
| |\ | | | | | More meaningful SystemVerilog/Verilog parser error messages | |||||
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index : iCE40/yosys | |
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