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| * Rename the generic "Syntax error" message from the Verilog/SystemVerilog ↵Udi Finkelstein2018-10-251-14/+14
| | | | | | | | | | | | | | parser into unique, meaningful info on the error. Also add 13 compilation examples that triggers each of these messages.
* | Improve read_verilog range out of bounds warningClifford Wolf2018-10-201-6/+6
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | Refactor code to avoid code duplication + added commentsRuben Undheim2018-10-203-134/+108
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* | Support for SystemVerilog interfaces as a port in the top level module + ↵Ruben Undheim2018-10-201-3/+105
| | | | | | | | test case
* | Fixed memory leakRuben Undheim2018-10-201-0/+1
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* Merge pull request #659 from rubund/sv_interfacesClifford Wolf2018-10-186-14/+353
|\ | | | | Support for SystemVerilog interfaces and modports
| * Handle FIXME for modport members without type directly in frontRuben Undheim2018-10-131-6/+8
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| * Documentation improvements etc.Ruben Undheim2018-10-132-8/+35
| | | | | | | | | | | | | | | | | | - Mention new feature in the SystemVerilog section in the README file - Commented changes much better - Rename a few signals to make it clearer - Prevent warning for unused signals in an easier way - Add myself as copyright holder to 2 files - Fix one potential memory leak (delete 'wire' if not in modport)
| * Fix build error with clangRuben Undheim2018-10-121-1/+1
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| * Support for 'modports' for System Verilog interfacesRuben Undheim2018-10-124-8/+89
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| * Synthesis support for SystemVerilog interfacesRuben Undheim2018-10-126-14/+243
| | | | | | | | This time doing the changes mostly in AST before RTLIL generation
* | Merge pull request #664 from tklam/ignore-verilog-protectClifford Wolf2018-10-181-0/+3
|\ \ | | | | | | Ignore protect endprotect
| * | ignore protect endprotectargama2018-10-161-0/+3
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* | Minor code cleanups in liberty front-endClifford Wolf2018-10-171-16/+5
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | Merge pull request #660 from tklam/parse-liberty-detect-ff-latchClifford Wolf2018-10-171-0/+17
|\ \ | | | | | | Handling ff/latch in liberty files
| * | detect ff/latch before processing other nodesargama2018-10-141-0/+17
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* | Merge pull request #638 from udif/pr_reg_wire_errorClifford Wolf2018-10-171-0/+12
|\ \ | |/ |/| Fix issue #630
| * Fixed issue #630 by fixing a minor typo in the previous commitUdi Finkelstein2018-09-251-2/+2
| | | | | | | | (as well as a non critical minor code optimization)
| * Merge branch 'master' into pr_reg_wire_errorUdi Finkelstein2018-09-1821-479/+1448
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| * | Fixed remaining cases where we check fo wire reg/wire incorrect assignmentsUdi Finkelstein2018-09-181-0/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | on Yosys-generated assignments. In this case, offending code was: module top(input in, output out); function func; input arg; func = arg; endfunction assign out = func(in); endmodule
* | | Improve Verific importer blackbox handlingClifford Wolf2018-10-071-2/+14
| | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | | Fix compiler warning in verific.ccClifford Wolf2018-10-051-0/+2
| | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | | Fix for issue 594.Tom Verbeure2018-10-021-1/+2
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* | | Add read_verilog $changed supportDan Gisselquist2018-10-011-1/+4
| | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | | Merge branch 'yosys-0.8-rc' of github.com:YosysHQ/yosysClifford Wolf2018-09-301-1/+1
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| * | | Fix handling of $past 2nd argument in read_verilogClifford Wolf2018-09-301-1/+1
| | |/ | |/| | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | | Add "read_verilog -noassert -noassume -assert-assumes"Clifford Wolf2018-09-243-6/+49
| | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | | Added support for ommited "parameter" in Verilog-2001 style parameter decl ↵Clifford Wolf2018-09-231-3/+9
|/ / | | | | | | | | | | in SV mode Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | Add "verific -L <int>" optionClifford Wolf2018-09-043-2/+16
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | Add "make coverage"Clifford Wolf2018-08-276-12/+10
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | Merge pull request #610 from udif/udif_specify_round2Clifford Wolf2018-08-231-16/+39
|\ \ | | | | | | More specify/endspecify fixes
| * | Fixed all known specify/endspecify issues, without breaking 'make test'.Udi Finkelstein2018-08-201-12/+12
| | | | | | | | | | | | | | | Some the of parser fixes may look strange but they were needed to avoid shift/reduce conflicts, due to the explicit parentheses in path_delay_value, and the mintypmax values without parentheses
| * | Yosys can now parse ↵Udi Finkelstein2018-08-201-10/+22
| | | | | | | | | | | | | | | | | | | | | https://github.com/verilog-to-routing/vtr-verilog-to-routing/blob/master/vtr_flow/primitives.v , (specify block ignored). Must use 'read_verilog -defer' due to a parameter not assigned a default value.
| * | A few minor enhancements to specify block parsing.Udi Finkelstein2018-08-151-2/+13
| | | | | | | | | | | | Just remember specify blocks are parsed but ignored.
* | | Added -no_dump_ptr flag for AST dump options in 'read_verilog'Udi Finkelstein2018-08-233-9/+20
| | | | | | | | | | | | | | | | | | This option disables the memory pointer display. This is useful when diff'ing different dumps because otherwise the node pointers makes every diff line different when the AST content is the same.
* | | Add "verific -work" help messageClifford Wolf2018-08-221-0/+7
| | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | | Add Verific -work parameterClifford Wolf2018-08-221-8/+18
| | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | | Add "verific -set-<severity> <msg_id>.."Clifford Wolf2018-08-161-14/+52
| | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | | Verific workaround for VIPER ticket 13851Clifford Wolf2018-08-161-0/+3
|/ / | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | Merge pull request #591 from hzeller/virtual-overrideClifford Wolf2018-08-157-23/+23
|\ \ | | | | | | Consistent use of 'override' for virtual methods in derived classes.
| * | Consistent use of 'override' for virtual methods in derived classes.Henner Zeller2018-07-207-23/+23
| | | | | | | | | | | | | | | | | | | | | | | | | | | o Not all derived methods were marked 'override', but it is a great feature of C++11 that we should make use of. o While at it: touched header files got a -*- c++ -*- for emacs to provide support for that language. o use YS_OVERRIDE for all override keywords (though we should probably use the plain keyword going forward now that C++11 is established)
* | | Merge pull request #590 from hzeller/remaining-file-errorClifford Wolf2018-08-151-15/+15
|\ \ \ | | | | | | | | Fix remaining log_file_error(); emit dependent file references in new…
| * | | Fix remaining log_file_error(); emit dependent file references in new line.Henner Zeller2018-07-201-15/+15
| |/ / | | | | | | | | | | | | | | | | | | There are some places that reference dependent file locations ("this function was called from ..."). These are now in a separate line for ease of jumping to it with the editor (behaves similarly to compilers that emit dependent messages).
* | | Merge pull request #513 from udif/pr_reg_wire_errorClifford Wolf2018-08-155-4/+57
|\ \ \ | | |/ | |/| Add error checking for reg/wire/logic misuse - PR now passes 'make test' (plus a new test)
| * | Modified errors into warningsUdi Finkelstein2018-06-054-7/+41
| | | | | | | | | | | | No longer false warnings for memories and assertions
| * | This PR should be the base for discussion, do not merge it yet!Udi Finkelstein2018-03-115-4/+23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | It correctly detects reg/wire mix and incorrect use on blocking,nonblocking assignments within blocks and assign statements. What it DOES'T do: Detect registers connected to output ports of instances. Where it FAILS: memorty nonblocking assignments causes spurious (I assume??) errors on yosys-generated "_ADDR", "_DATA", "EN" signals. You can test it with tests/simple/reg_wire_error.v (look inside for the comments to enable/disable specific lines)
* | | Merge pull request #562 from udif/pr_fix_illegal_port_declClifford Wolf2018-08-151-3/+6
|\ \ \ | | | | | | | | Detect illegal port declaration, e.g input/output/inout keyword must …
| * | | Detect illegal port declaration, e.g input/output/inout keyword must be the ↵Udi Finkelstein2018-06-061-3/+6
| | | | | | | | | | | | | | | | first.
* | | | Fixed use of char array for string in blifparse error handlingClifford Wolf2018-08-081-5/+5
| | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | | | Report error reason on same line as syntax error.litghost2018-08-081-6/+9
| | | | | | | | | | | | | | | | Signed-off-by: litghost <537074+litghost@users.noreply.github.com>
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